NDLI: Random sampling for on-chip characterization of standard-cell propagation delay

Content Provider	IEEE Xplore Digital Library
Author	Maggioni, S. Veggetti, A. Bogliolo, A. Croce, L.
Copyright Year	2003
Description	Author affiliation: STMicroelectron., Agrate, Italy (Maggioni, S.; Veggetti, A.)
Abstract	We present a methodology for on-chip characterization of the pin-to-pin propagation delay of single standard cells. A periodic waveform is provided to an input pin of the standard cell under characterization, while keeping all other inputs at non-controlling logic values. Simultaneous random sampling is then applied to input and output periodic waveforms, and propagation delay measures are obtained from the joint signal probabilities of the samples. The proposed technique is suitable for on-chip implementation because it is simple and it doesn't require timing-accurate control signals. On the other hand, on-chip measurements can be applied to a large number of cells working in different operating conditions, providing valuable information for characterizing and validating timing models. A test chip has been realized in a 0.18 /spl mu/m embedded NVM CMOS technology, and used to monitor the sub-nanosecond timing behavior of a standard cell library during process development.
Sponsorship	IEEE Electron Device Soc. (EDS) IEEE Components, Packaging & Manuf. Technol. Soc. (CPMT) ACM ACM/sigDA
Starting Page	41
Ending Page	45
File Size	271762
Page Count	5
File Format	PDF
ISBN	0769518818
DOI	10.1109/ISQED.2003.1194707
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2003-03-24
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Sampling methods Propagation delay Timing CMOS technology Logic Semiconductor device measurement Semiconductor device modeling Testing CMOS process Standards development
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
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3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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