NDLI: Transistor modeling for the VDSM era

Content Provider	IEEE Xplore Digital Library
Author	Shur, M.S. Fjeldly, T.A. Ytterdal, T.
Copyright Year	2000
Description	Author affiliation: CIEEM, Rensselaer Polytech. Inst., Troy, NY, USA (Shur, M.S.)
Abstract	We review field effect transistor modeling with emphasis on device parameter extraction for testing. We consider the physics-based universal charge control model, which allows us to describe the subthreshold, the weak inversion, and the strong inversion regimes in MOSFETs using a relatively small set of parameters, most of which are related to the device structure or fabrication process. This small parameter set makes the task of parameter extraction easier. The model accounts for velocity saturation, finite output conductance in saturation, drain induced barrier lowering, kink effect, floating body effect, and subthreshold leakage. The model has been applied to MOSFETs, SOI transistors, GaAs MESFETs, GaAs based HEMTs, amorphous, polysilicon and organic TFTs, AlGaN/GaN HEMTs, and to new emerging heterodimensional transistors. For compound semiconductor devices, additional effects, such as frequency dispersion and temperature dependence of model parameters, and gate leakage current, including hot-carrier leakage, have been accounted for.
Starting Page	37
Ending Page	43
File Size	162682
Page Count	7
File Format	PDF
ISBN	0769505252
DOI	10.1109/ISQED.2000.838851
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2000-03-22
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	MOSFETs Parameter extraction Gallium arsenide HEMTs MODFETs FETs Testing Fabrication Subthreshold current MESFETs
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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