NDLI: A 5.2 nS cycle time floating point unit macrocell

Content Provider	IEEE Xplore Digital Library
Author	Hossain, R. Herbert, J.C. Gouger, J.F. Bechade, R.
Copyright Year	1998
Description	Author affiliation: Mentor Graphics Corporation, Warren, NJ, USA (Hossain, R.)
Abstract	This paper describes the structured custom design of a pipelined floating point unit (FPU) macrocell. The core of the floating point unit is a multiplier-accumulator (MAC) block which can execute a 2 clock cycle addition, subtraction or multiplication, or, a 4 cycle multiply-accumulate operation. The floating point unit supports both floating point and signed integer arithmetic, as well as, float-to-int, int-to-float, and, float-to-float conversions between different mantissa widths. The simulated cycle time for the FPU with typical process parameters at 3.3 V and 85° C is 5.2 nS. The rapid completion of the design was made possible by leveraging an existing generator based datapath module library. Approximately 25 man months were required from initial customer specification until final physical assembly of the structured custom block. The floating point unit is implemented with 165,000 transistors in a 0.35µm, 4 metal CMOS process and occupies 2.45 mm × 2.55 mm.
Starting Page	136
Ending Page	139
File Size	432102
Page Count	4
File Format	PDF
DOI	10.1109/ESSCIR.1998.186227
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1998-09-22
Publisher Place	The Netherlands
Access Restriction	Subscribed
Rights Holder	Editions Frontieres
Subject Keyword	Macrocell networks Adders Clocks Libraries Circuits Graphics Floating-point arithmetic Assembly Transistors CMOS process
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Mr. Siddhartha Mukherjee siddhartha@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	ndl-support@iitkgp.ac.in
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9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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