NDLI: A VLSI link-level controller

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2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers

2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC)

2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers

2012 IEEE International Solid-State Circuits Conference

2011 IEEE International Solid-State Circuits Conference

2010 IEEE International Solid-State Circuits Conference - (ISSCC)

2009 IEEE International Solid-State Circuits Conference - Digest of Technical Papers

2008 IEEE International Solid-State Circuits Conference - Digest of Technical Papers

2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers

ISSCC. 2005 IEEE International Digest of Technical Papers. Solid-State Circuits Conference, 2005.

2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519)

2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC.

2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315)

2001 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC (Cat. No.01CH37177)

2000 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.00CH37056)

1999 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC. First Edition (Cat. No.99CH36278)

1998 IEEE International Solid-State Circuits Conference. Digest of Technical Papers, ISSCC. First Edition (Cat. No.98CH36156)

1997 IEEE International Solids-State Circuits Conference. Digest of Technical Papers

1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC

Proceedings ISSCC '95 - International Solid-State Circuits Conference

Proceedings of IEEE International Solid-State Circuits Conference - ISSCC '94

1993 IEEE International Solid-State Circuits Conference Digest of Technical Papers

1992 IEEE International Solid-State Circuits Conference Digest of Technical Papers

1991 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

1990 37th IEEE International Conference on Solid-State Circuits

IEEE International Solid-State Circuits Conference, 1989 ISSCC. Digest of Technical Papers

1988 IEEE International Solid-State Circuits Conference, 1988 ISSCC. Digest of Technical Papers

1987 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

1986 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

1985 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

1984 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

Volume XXVII - 1984

Foreword the fourth decade era

Table of contents

Session 1 custom and semi-custom design techniques [breaker page]

An integrated modular and standard cell IC design method

A comparison of mixed gate array and custom IC design methods

Cascode voltage switch logic: A differential CMOS logic family

A synthesis program for operation amplifiers

Computer generation of digital filter banks

Use of E-beam for random access read and write of digital test signals

Session 2 image sensors [breaker page]

MOS imaging with random noise suppression

A line transfer color image sensor with 576×462 pixels

A 488×430 interline transfer CCD imager with integrated exposure and blooming control

An interline transfer CCD imager

A 3456-element CCD sensor with serpentine shift registers

A 5732-element 1.2" linear CCD imager

Session 3 digital GaAs circuits [breaker page]

A 1K-gate GaAs gate array

GaAs heterojunction bipolar 1K gate array

A 3ns GaAs 4K×1b SRAM

A GaAs 4Kb SRAM with direct coupled FET logic

A subnanosecond HEMT 1Kb SRAM

4.5GHz frequency dividers using GaAs/(Ga,AI) as heterojunction bipolar transistors

A 1GHz 50mW dual modulus divider IC using source coupled FET logic

Session 4 data acquisition circuits [breaker page]

A bulk CMOS 20MS/s 7b flash ADC

An 8b 100MS/s flash ADC

A multi step parallel 10b 1.5µs ADC

A ratio independent algorithmic A/D conversion technique

A self calibrating 12b 12µs CMOS ADC

A trimless 16b digital potentiometer

Session 5 formal opening of conference [breaker page]

A positive program for world cooperation

Session 7 high speed analog circuits [breaker page]

A GaAs monolithic voltage controlled oscillator

Fine line NMOS transresistance amplifiers

Distributed cascode amplifier and noise figure modeling of an arbitrary amplifier configuration

Computer-aided design of nonlinear microwave ICs

Session 8 signal and data processing circuits [breaker page]

A 45ns 16×16 CMOS multiplier

A 25/50MHz dual-mode parallel multiplier/accumulator

A 16ns 2K×8b CMOS SRAM

A CMOS floating point multiplier

A CMOS/SOS multiplier

Session 8A 256K/1Mb DRAMs:I [breaker page]

A 59ns 256K DRAM using $LD^{3}technology$ and double level metal

A 70ns 256K DRAM with bitline shielding structure

A capacitance coupled bit line cell for Mb level DRAMs

Triple poly II DRAM memory cell

A submicron VLSI memory with a 4b-at-a-time built-in ECC circuit

A 128K word × 8b DRAM

Session 9 dedicated signal processors [breaker page]

A CCD matrix matrix product parallel processor

A single-chip 20 channel speech spectrum analyzer

An integrated phoneme speech synthesizer

A monolithic programmable speech synthesizer with voice recognition

A single chip LPC vocoder

A CMOS CCD video delay line

Wafer scale integration

Testing methodology for VLSI

System requirements for GaAs digital ICs

High speed A/D conversion

1Mb DRAM alternatives

Session 10 nonvolatile memories [breaker page]

256Kb CMNOS EPROM

A 64Kb CMOS EEROM with on-chip ECC

A 55ns CMOS EEPROM

An 80ns 1Mb ROM

A programmable 256K CMOS EPROM with on-chip test circuits

Session 11 scaling and performance aspects of technology [breaker page]

Integrated 84ps ECL with $I^{2}L$

Merged current mode logic

1.5µm scaled CMOS microcomputer technology

Performance limits of NMOS and CMOS

Physical limits of VLSI DRAMs

Stability and soft error rates of SRAM cells

Optimal interconnect circuits for VLSI

Session 12 microprocessors and microcontrollers [breaker page]

A 32b NMOS microprocessor with a large register file

A 5V-only single chip microcomputer with nonvolatile SRAM

A VLSI communication processor designed for testability

A VLSI superminicomputer CPU

A 32b bus interface chip

A 32b microprocessor with on chip virtual memory management

A pipelined 32b NMOS microprocessor

Session 13 MODEMs [breaker page]

A CMOS ethernet serial interface chip

Signaling pickoff filter for FDM

A 300-baud frequency shift keying MODEM

An asynchronous FSK MODEM

A 1200 baud FSK CMOS MODEM

A 1200b/s QPSK duplex MODEM

A VLSI link-level controller

Session 14 overview signal processing [breaker page]

A CCD TV signal processor

An integrated CMOS-CCD TV ghost canceler

Facsimile shading corrector

A 40MHz 308Kb CCD video memory

A VLSI image pipeline processor

A digital radio command link for implantable biotelemetry applications

Session 15 static RAMs [breaker page]

A 46ns 256K CMOS SRAM

A 30ns 64K CMOS RAM

A 25ns 64K SRAM

A 2.3ns access time 4K ECL RAM

A 20ns 64K CMOS SRAM

A 28ns CMOS SRAM with bipolar sense amplifiers

A 20ns 64K NMOS RAM

Session 16 telecommunication system ICs [breaker page]

A single-chip high-voltage shallow-junction BORSHT-LSI

A programmable CMOS dual channel interface processor

A 150mW subscriber line board controller

A 200Kb/s burst mode transceiver with two-bridge tap equalizer

A burst-mode LSI equalizer with analog-digital building blocks

A regenerator chip set for high speed digital transmission

A CMOS line equalizer for a digital subscriber loop

Status, future and standardization of EEPROMs

Technology for data transport in an office environment

High speed analog ICs

Semi-custom analog LSI design trends and directions

Opportunities and limitations in ultra high speed SRAMs

Session 17 semi-custom arrays [breaker page]

A CMOS 12K gate array with flexible 10Kb memory

A sub nanosecond 8K-gate CMOS/SOS gate array

A 2µm poly-gate CMOS analog/digital array

An ECL field programmable logic array

A VLSI delay commutator for FFT implementation

An EEPROM for microprocessors and custom logic

Session 18 256K/1Mb DRAMs:II [breaker page]

A 256K DRAM with descrambled redundancy test capability

A 256K NMOS DRAM

A 288Kb CMOS pseudo SRAM

A sub 100ns 256K DRAM in CMOS III technology

Shared word line DRAM-cell

An experimental 1Mb DRAM with on-chip voltage limiter

Session 19 general purpose analog circuits [breaker page]

An analog array processor

A monolithic P-channel JFET QUAD operational amplifier

A power BiMOS with integral high current PNP transistor

A fahrenheit temperature sensor

A 400MHz 6b DAC

An 8b monolithic ADC

A decade of outstanding papers 1968-1977

The 1984 IEEE Cledo Brunetti award

Beatrice Winner Award for editorial excellence

Outstanding contributed papers

Executive Committee 1984 ISSCC

Program committee 1984 ISSCC

Far East Program Committee 1984 ISSCC

European Program Committee 1984 ISSCC

Conference timetable

1983 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

1982 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

1981 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

1980 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

1979 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

1978 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

1977 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

1976 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

1975 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

1974 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

1973 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

1972 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

1971 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

1970 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

1969 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

1968 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

1967 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

1966 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

1965 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

1964 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

1963 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

1962 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

1961 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

1960 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

1959 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

1958 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

1957 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

1956 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

1955 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

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Indian Institute of Technology Kharagpur
Kharagpur, West Bengal, India | PIN - 721302

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03222 282435
Mail: ndl-support@iitkgp.ac.in

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Mr. Siddhartha Mukherjee siddhartha@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	ndl-support@iitkgp.ac.in
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9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in