NDLI: A 1.0 GHz single-issue 64 b powerPC integer processor

Please wait, while we are loading the content...

2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers

2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC)

2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers

2012 IEEE International Solid-State Circuits Conference

2011 IEEE International Solid-State Circuits Conference

2010 IEEE International Solid-State Circuits Conference - (ISSCC)

2009 IEEE International Solid-State Circuits Conference - Digest of Technical Papers

2008 IEEE International Solid-State Circuits Conference - Digest of Technical Papers

2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers

ISSCC. 2005 IEEE International Digest of Technical Papers. Solid-State Circuits Conference, 2005.

2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519)

2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC.

2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315)

2001 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC (Cat. No.01CH37177)

2000 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.00CH37056)

1999 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC. First Edition (Cat. No.99CH36278)

1998 IEEE International Solid-State Circuits Conference. Digest of Technical Papers, ISSCC. First Edition (Cat. No.98CH36156)

1998 ieee international solid-state circuits conference. digest of technical papers, isscc. first edition [front cover and table of contents]

Challenges in semiconductor technology for multi-megabit network services

GSM and beyond-the future of the access network

The Global Positioning System: challenges in bringing GPS to mainstream consumers

A 100 mm/sup 2/ 0.95 W single-chip MPEG2 MP@ML video encoder with a 128GOPS motion estimator and a multi-tasking RISC-type controller

A 1.2 W single-chip MPEG2 MP@ML video encoder LSI including wide search range motion estimation and 81 MOPS controller

A 60 mW MPEG4 video codec using clustered voltage scaling with variable supply-voltage scheme

0.5 /spl mu/m CMOS circuits performing OFDM demodulation and channel estimation/correction for digital terrestrial TV applications

A power-efficient single-chip OFDM demodulator and channel decoder for multimedia broadcasting

A 900 MHz transceiver chipset for two-way paging applications

CMOS IF transceiver for narrowband PCS

A single-chip CMOS transceiver for DCS-1800 wireless communications

A 3.6 V 4 W 0.2cc Si power-MOS-amplifier module for GSM handset phones

A 2.7-5.5 V 0.2-1 W BiCMOS RF driver amplifier IC with closed-loop power control and biasing

An IC for linearizing RF power amplifiers using envelope elimination and restoration

An audio DAC with 90 dB linearity using MOS to metal-metal charge transfer

A 1.5 V, 4.1 mW dual channel audio delta-sigma D/A converter

A 113 dB SNR oversampling DAC with segmented noise-shaped scrambling

A 100 kHz 9.6 mW multi bit /spl Delta//spl Sigma/ DAC and ADC using noise shaping dynamic elements matching with tree structure

An Eight-order Bandpass /spl delta/ /spl sigma/l Modulator For A/D Conversion In Digital Radio

A 900 mV 40 /spl mu/W switched opamp /spl Delta//spl Sigma/ modulator with 77 dB dynamic range

A configurable DRAM macro design for 2112 derivative organizations to be synthesized using a memory generator

An ASIC library granular DRAM macro with built-in self test

500 Mb/s non-precharged data bus for high-speed DRAM

A 220 mm/sup 2/ 4 and 8 bank 256 Mb SDRAM with single-sided stitched WL architecture

A 255 Mb SDRAM with subthreshold leakage current suppression

A 1 Gb SDRAM with ground level precharged bitline and non-boosted 2.1 V word line

Beyond superscalar RISC, what next? An almost unbiased view

A sub-0.1 /spl mu/m circuit design with substrate-over-biasing [CMOS logic]

Statistical circuit characterization for deep-submicron CMOS designs

Multi-chip module with optical interconnection for parallel processor system

A 1M synapse self-learning digital neural network chip

Bulk spin quantum computation: toward large-scale quantum computation

A 85 /spl mu/W asynchronous filter-bank for a digital hearing aid

A 1 Mbs energy/security scalable encryption processor using adaptive width and supply

A 1 V 350 /spl mu/W voice-controlled H.263 video decoder for portable applications

A 0.4 W mixed-signal digital storage oscilloscope processor with Moire prevention, embedded 393 kb RAM and 50 M sample/s 8b ADC

An 0.8 /spl mu/m CMOS mixed analog-digital integrated audiometric system

A high precision 1024-point FFT processor for 2D convolution

A 115 mW CMOS GPS receiver

A 900 MHz/1.8 GHz CMOS receiver for dual band applications

A direct conversion L-band tuner for digital DBS

A 2 V, 600 mA, 1 GHz, BiCMOS super-regenerative receiver

A global car radio IC with inaudible signal quality checks

A fully integrated CMOS 900 MHz LNA utilizing monolithic transformers

4 GHz and 13 GHz tuned amplifiers implemented in a 0.1 /spl mu/m CMOS technology on SOI and SOS substrates

A single-ended 12 b 20 M sample/s self-calibrating pipeline A/D converter

Digital background calibration of a 10 b 40 M sample/s parallel pipelined ADC

Analog background calibration of a 10 b 40 Msample/s parallel pipelined ADC

A continuously-calibrated 10 M sample/s 12 b 3.3 V ADC

8 b 75 M sample/s 70 mW parallel pipelined ADC incorporating double sampling

A 5.75 b 350 M sample/s or 6.75 b 150 M sample/s reconfigurable flash ADC for a PRML read channel

A 400 M sample/s 6b CMOS folding and interpolating ADC

A CMOS 6b 400 M sample/s ADC with error correction

A process independent 800 MB/s DRAM bytewide interface featuring command interleaving and concurrent memory operation

A 640 MB/s bi-directional data strobed, double-data-rate SDRAM with a 40 mW DLL circuit for a 256 MB memory system

Source synchronization and timing Vernier techniques for 1.2 GB/s SLDRAM interface

A 2.6 GB/s multi-purpose chip-to-chip interface

PRD-based global-mean-time signaling for high-speed chip-to-chip communications

A 200 mW 3.3 V CMOS color camera IC producing 352/spl times/288 24 b video at 30 frames/s

A single-chip 306/spl times/244-pixel CMOS NTSC video camera

A 37/spl times/28 mm/sup 2/ 600k-pixel CMOS APS dental X-ray camera-on-a-chip with self-triggered readout

A CMOS imager with on-chip variable resolution for light-adaptive imaging

A 256/spl times/256 CMOS imaging array with wide dynamic range pixels and column-parallel digital output

A 1/2 inch 1.3 M-pixel progressive-scan IT-CCD for still and motion picture applications

A 1 mm 50 K-pixel IT CCD image sensor for miniature camera system

A 3.7/spl times/3.7 /spl mu/m/sup 2/ square pixel CMOS image sensor for digital still camera application

Toward sub 1 V analog integrated circuits in submicron standard CMOS technologies

0.5 V 320 MHz 8 b multiplexer/demultiplexer chips based on a gate array with regular-structured DTMOS/SOI

A sub-1 V triple-threshold CMOS/SIMOX circuit for active power reduction

A CMOS scheme for 0.5 V supply voltage with pico-ampere standby current

Multiple-valued logic-in-memory VLSI based on a floating-gate-MOS pass-transistor network

1.5 TXPS convolver using 5b analog flash for real-time large-kernel image filtering

A 70 Mb/s variable-rate 1024-QAM cable receiver IC with integrated 10 b ADC and FEC decoder

A 10 Gb/s SiGe bipolar framer/demultiplexer for SDH systems

A 2 V 120 mA 25 Gb/s 2/spl times/2 crosspoint switch in InP-HBT technology

A 3.3 V 20-channel 500 Mb/s/ch optical receiver with integrated optical detectors in 1.2 mm GaAs

A 100 Mb/s CMOS 100Base-T4 Fast Ethernet transceiver for category 3, 4 and 5 UTP

A 10/100 Mb/s CMOS Ethernet transceiver for 10BaseT, 100BaseTX, and 100BaseFX

A 10 b 250 M sample/s CMOS DAC in 1 mm/sup 2/

A 12 b accuracy 300 Msample/s update rate CMOS DAC

A practical quality factor tuning scheme for IF and high-Q continuous-time filters

A 2.7 V 200 kHz 49 dBm-IIP3 28 nV//spl radic/Hz input-referred-noise fully-balanced gm-C filter IC

A 20-800 MHz relaxation oscillator with automatic swing control

A fully integrated VCO at 2 GHz

A fully integrated 2.7 V 0.35 /spl mu/m CMOS VCO for 5 GHz wireless applications

A 1.0 GHz single-issue 64 b powerPC integer processor

Design tradeoffs in stall-control circuits for 600 MHz instruction queues

A commercial multithreaded RISC processor

A 450 MHz IA32 P6 family microprocessor

A 200 MHz 32 b 0.5 W CMOS RISC microprocessor

A 480 MHz RISC microprocessor in a 0.12 /spl mu/m L/sub eff/ CMOS technology with copper interconnects

A 0.25 mm x86 microprocessor with a 100 MHz socket 7 interface

RF circuit design aspects of spiral inductors on silicon

Silicon-on-silicon integration of a GSM transceiver with VCO resonator

A 3.5 mW 2.5 GHz diversity receiver and a 1.2 mW 3.6 GHz VCO in silicon-on-anything

K-band Si MMIC amplifier and mixer using three-dimensional masterslice MMIC technology

RF perspective of sub-tenth-micron CMOS

Fractal capacitors

Multi-GHz A/D converter using resonant-tunnelling multiple-valued logic circuits

Active CMOS biochips: an electro-addressed DNA probe

An active charge-cancellation system for switched-capacitor sensor interface circuits

An IEEE 1451 standard transducer interface chip

A 16 /spl mu/A interface circuit for a capacitive-flow sensor

Monolithic 4-20 mA isolating current replicator using GMR resistors

A 256/spl times/256 BCAST motion detector with simultaneous video output

A robust, 1.8 V 250 /spl mu/W direct-contact 500 dpi fingerprint sensor

A 200 MHz 1.2 W 1.4 GFLOPS microprocessor with graphic operation unit

A 1.2 W 2.16 GOPS/720 MFLOPS embedded superscalar microprocessor for multimedia applications

An 800 MOPS 110 mW 1.5 V parallel DSP for mobile multimedia processing

A 667 MHz RISC microprocessor containing a 6.0 ns 64 b integer multiplier

A 2.7 ns 0.25 /spl mu/m CMOS 54/spl times/54 b multiplier

A low-cost 300 MHz RISC CPU with attached media processor

A 10 Gb/s Si-bipolar TX/RX chipset for computer data transmission

A single chip 2.4 Gb/s CMOS optical receiver IC with low substrate crosstalk preamplifier

A 4.25 Gb/s CMOS fiber channel transceiver with asynchronous binary tree-type demultiplexer and frequency conversion architecture

A two-chip receiver for short haul links up to 3.5 Gb/s with PIN-preamp module and CDR-DMUX

A jitter-tolerant 4.5 Gb/s CMOS interconnect for digital display

95 GHz f/sub T/ self-aligned selective epitaxial SiGe HBT with SMI electrodes [optical fiber communication equipment]

40 Gb/s analog IC chipset for optical receiver using SiGe HBTs

Analog video line driver with adaptive impedance matching

A 100 MHz 50 /spl Omega/-45 dB distortion 3.3 V CMOS line-driver for Ethernet and fast Ethernet networking applications

A 300/spl deg/C dynamic-feedback instrumentation amplifier

A /spl plusmn/2.45 V-swing CMOS telescopic operational amplifier

A 2 V 7.2/spl deg/ jitter AM-suppression CMOS amplifier using current-mode hybrid magnitude control

5 Gsample/s track-hold and 3 Gsample/s quasi-sample-hold ICs

Fully-parallel 25 MHz 2.5 Mb CAM

1 M-cell 6b/cell analog flash memory for digital storage

An 8 b resolution 360 /spl mu/s write time nonvolatile analog memory based on differentially balanced constant-tunneling-current scheme (DBCS)

A 3.3 V 133 MHz 32 Mb synchronous mask ROM [in CMOS]

A 33 GB/s 13.4 Mb integrated graphics accelerator and frame buffer

Compression/decompression DRAM for unified memory systems: a 16 Mb, 200 MHz, 90% to 50% graphics-bandwidth reduction prototype

A 128 Mb early prototype for gigascale single-electron memories

Synonym hit RAM; a 500 MHz 1.5 ns CMOS SRAM macro with 576 b parallel comparison and parity check functions

64 kB sum-addressed-memory cache with 1.6 ns cycle and 2.6 ns latency

A 3.6 mW 1.4 V SRAM with non-boosted, vertical bipolar bitline contact memory cell

A 1 V 0.9 mW at 100 MHz 2 k/spl times/16 b SRAM utilizing a half-swing pulsed-decoder and write-bus architecture in 0.25 /spl mu/m dual-Vt CMOS

A 833 Mb/s 2.5 V 4 Mb double data rate SRAM

A 450 MHz 512 kB second-level cache with a 3.6 GB/s data bandwidth

A 1.8 ns access, 550 MHz 4.5 Mb CMOS SRAM

An up-conversion loop transmitter IC for digital mobile telephones

A /spl Delta//spl Sigma/PLL for 14 b 50 ksample/s frequency-to-digital conversion of a 10 MHz FM signal

An I/Q active balanced harmonic mixer with IM2 cancelers and a 45/spl deg/ phase shifter

A 1 V multi-gigahertz RF mixer core in 0.5 /spl mu/m CMOS

A fully integrated CMOS DCS-1800 frequency synthesizer

A 5 GHz-band BiCMOS up/down-converter chip for GMSK modulation wireless systems

A 300 Mb/s BiCMOS EPR4 read channel for magnetic hard disks

An analog EPR4 Viterbi detector in read channel IC for magnetic hard disks

540 MHz 21 mW MDFE equalizer and detector in 0.25 /spl mu/m CMOS

A CMOS DVD 4/spl times/ speed read channel programmable over 5 octaves

A 240 Mb/1 W CMOS EPRML read channel LSI for hard disk drives

A 245 Mb/s EPR4 read/write channel with digital timing recovery

A Reed-Solomon Product-Code (RS-PC) decoder for DVD applications

A CMOS analog timing recovery circuit for 180 Mb/s PRML detectors

A 600 MHz CMOS PLL microprocessor clock generator with a 1.2 GHz VCO

Clocking design and analysis for a 600 MHz Alpha microprocessor

An adaptive digital deskewing circuit for clock distribution networks

Device-deviation tolerant over-1 GHz clock distribution scheme with skew-immune race-free impulse latch circuits

A noise-immune GHz-clock distribution scheme using synchronous distributed oscillators

1997 IEEE International Solids-State Circuits Conference. Digest of Technical Papers

1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC

Proceedings ISSCC '95 - International Solid-State Circuits Conference

Proceedings of IEEE International Solid-State Circuits Conference - ISSCC '94

1993 IEEE International Solid-State Circuits Conference Digest of Technical Papers

1992 IEEE International Solid-State Circuits Conference Digest of Technical Papers

1991 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

1990 37th IEEE International Conference on Solid-State Circuits

IEEE International Solid-State Circuits Conference, 1989 ISSCC. Digest of Technical Papers

1988 IEEE International Solid-State Circuits Conference, 1988 ISSCC. Digest of Technical Papers

1987 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

1986 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

1985 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

1984 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

1983 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

1982 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

1981 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

1980 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

1979 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

1978 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

1977 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

1976 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

1975 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

1974 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

1973 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

1972 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

1971 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

1970 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

1969 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

1968 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

1967 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

1966 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

1965 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

1964 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

1963 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

1962 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

1961 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

1960 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

1959 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

1958 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

1957 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

1956 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

1955 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

Central Library (ISO-9001:2015 Certified)
Indian Institute of Technology Kharagpur
Kharagpur, West Bengal, India | PIN - 721302

See location in the Map
03222 282435
Mail: support@ndl.gov.in

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Libarray of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in