NDLI: A 10-bit 20-Msample/s 49mW CMOS pipelined A/D converter

Content Provider	IEEE Xplore Digital Library
Author	Yongjian Tang Lenian He Ning Xie Xi Chen Kun Yin Xiaolang Yan
Copyright Year	2004
Description	Author affiliation: Inst. of VLSI Design, Zhejiang Univ., Hangzhou, China (Yongjian Tang; Lenian He; Ning Xie; Xi Chen; Kun Yin; Xiaolang Yan)
Abstract	A 10-bit 20-Msample/s CMOS pipelined analog-to-digital converter (ADC) is proposed, which is implemented in a 0.6/spl mu/m double-poly double-metal CMOS process. The digital correction technique is used to relax the offset requirement of the comparators. To reduce signal-dependent charge injection and substrate noise injection, the bottom-plate sampling technology is applied. A sample-and-hold amplifier (SHA) is also used to improve the signal-to-noise and distortion ratio (SNDR) performance and the linearity of ADC. The circuit is simulated by the Hspice software which is based on CSMCs library of 0.6/spl mu/m mixed-signal CMOS model. The simulation results reveal that the ADC designed with this method achieves the SNDR of 58dB at full speed of 20MHz when input frequency is 5MHz. Furthermore, the ADC consumes 49mW power at 5V supply voltage with a low power operational transconductance amplifier (OTA) and the dynamic comparators.
Starting Page	1526
Ending Page	1529
File Size	798294
Page Count	4
File Format	PDF
ISBN	078038511X
DOI	10.1109/ICSICT.2004.1436903
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2004-10-18
Publisher Place	China
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	CMOS process Circuit simulation Analog-digital conversion Noise reduction Circuit noise Signal sampling CMOS technology Distortion Linearity Software libraries
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
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3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Mr. Siddhartha Mukherjee siddhartha@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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