NDLI: Advanced channel materials for the semiconductor industry

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2015 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)

New game-changing product applications enabled by SOI

Sustaining the silicon revolution: From 3-D transistors to 3-D integration

Smart power technologies on SOI

ESD protection design with latchup-free immunity in 120V SOI process

Key parameters of BiMOS ESD protection device for UTBB FDSOI advanced technology

A −1.8V to 0.9V body bias, 60 GOPS/W 4-core cluster in low-power 28nm UTBB FD-SOI technology

The missing XDXMOS found! — A SOTB circuit acceleration technique using front and back gate interaction

Negative capacitance in ferroelectric materials and implications for steep transistors

A ΔVt 0.2V to 1V $0.01mm^{2}$ 9.7nW voltage reference in 65nm LP/GP CMOS

Towards ultra-low-voltage wideband noise-cancelling LNAs in 28nm FDSOI

Advantages of subthreshold operation of asymmetric self-cascode SOI transistors aiming at analog circuit applications

A 145mV to 1.2V single ended level converter circuit for ultra-low power low voltage ICs

A 10 kgates sub-threshold stream cipher in 180 nm with 6.1 kHz frequency 70 nA total current and 46 nA leakage at 0.33 V

Single-well design in FDSOI technology: Towards energy-efficient ultra-wide voltage range digital circuits

Essential edge protection techniques for successful multi-wafer stacking

V self-adjusting tri-gate nanowire MOSFET for stability improvement of SRAM cell operating at 0.1 V

Engineered substrates for Moore and more than Moore's law: Device scaling: Entering the substrate era

300 mm InGaAsOI substrate fabrication using the Smart $Cut^{TM}$ technology

Systematic evaluation of SOI Buried Oxide reliability for partially depleted and fully depleted applications

Low voltage devices and circuits for energy-starved systems

A 23 nW CMOS ultra-low power temperature sensor operational from 0.2 V

Robust subthreshold level conversion

Can we connect trillions of IoT sensors in a sustainable way? A technology/circuit perspective (Invited)

IoT and the cloud: A hacked personality and an empty battery head-ache or an intuitive environment to make our lives easier?

Challenge of MTJ-based nonvolatile logic-in-memory architecture for ultra low-power and highly dependable VLSI computing

Enhanced low voltage digital & analog mixed-signal with 28nm FDSOI technology

Technology scaling: The $CoolCube^{TM}$ paradigm

Emerging 3DVLSI: Opportunities and challenges

Logic/memory hybrid 3D sequentially integrated circuit using low thermal budget laser process

From nanodevices to nanosystems: The N3XT information technology

Monolithic three-dimensional integration for memory scaling and neuromorphic computing

Nanowire FET design for 7-nm SOI-CMOS technology

On the T-RAM and FED-RAM memory mechanism

Asynchronous and synchronous designs for low-power FDSOI CMOS process optimized for subthreshold operation at 0.3V V

Analog performance improvement of self-cascode structures composed by UTBB transistors using back gate bias

CMOS-compatible FDSOI bipolar-enhanced tunneling FET

Silicon-on-Ferroelectric-Insulator — A comparative analysis of the partially and fully depleted devices

Low voltage ripple carry adder with low-granularity dynamic forward back-biasing in 28 nm UTBB FD-SOI

Minimum-energy point design in FDSOI Regular-V

Analysis of deeply scaled multi-gate devices with design centering across multiple voltage regimes

Monolithic 3D layout using 2D EDA for embedded memory-rich designs

Preliminary steps towards implementing intimate 3D-IC stacking with layer transfer and atomic bonding methods

Opportunities and challenges of nanowire-based CMOS technologies

Performance trade-offs in FinFET and gate-all-around device architectures for 7nm-node and beyond

Quasi-static analytical model for the dynamic operation of triple-gate junctionless nanowire transistors

Transconductance hump in vertical gate-all-around tunnel-FETs

Comparative simulation study on MoS2 FET and CMOS transistor

A soft error tolerant 4T gain-cell featuring a parity column for ultra-low power applications

Impact of technology and voltage scaling on LEON3 processor performance and energy

Subthreshold capable, asynchronous FPGA in a 14nm SOI process

A 300nW near-threshold 187.5–500 kHz programmable clock generator for ultra low power SoCs

Epitaxial layer transfer technology and application

Ultrathin chips for flexible electronics and 3D ICs

Switch branch in trap-rich RFSOI with 84 dBm off-state IP3

Comparative study of parasitic elements on RF FoM in 28 nm FD SOI and bulk technologies

SiGe-on-insulator symmetric lateral bipolar transistors

Extending the bandwidth of Piezo-Electric energy harvesting through the use of Bias Flip

Optimization of gate controlled diode in rectenna for high efficiency RF energy harvesting

0.8-V rail-to-rail operational amplifier with near-V gain-boosting stage fabricated in FinFET technology for IoT sensor nodes

Modified ELTRAN® — A game changer for Monolithic 3D

Power, performance, and cost comparisons of monolithic 3D ICs and TSV-based 3D ICs

128 × 96 Pixel-parallel three-dimensional integrated CMOS image sensors with 16-bit A/D converters: By direct bonding with embedded Au electrodes

Guidelines on 3DVLSI design regarding the intermediate BEOL process influence

Improving performance in near-threshold circuits using 3D IC technology

Advanced channel materials for the semiconductor industry

Special characterization techniques for advanced FDSOI process

Impact of source/drain silicon cap on FDSOI SiGe pMOSFET performance

Experimental study on quantum mechanical effect for insensitivity of threshold voltage against temperature variation in strained SOI MOSFETs

Full front and back split C-V characterization of CMOS devices from 14nm node FDSOI technology

Impact of supercoupling effect on mobility enhancement in UTBB SOI in dynamic threshold mode

Low power design: Ramping to production

0.5-V 350-ps 28-nm FD-SOI SRAM array with dynamic power-supply 5T cell

A 1kb single-side read 6T sub-threshold SRAM in 180 nm with 530 Hz frequency 3.1 nA total current and 2.4 nA leakage at 0.27 V

Design insights for reliable energy efficient OxRAM-based flip-flop in 28nm FD-SOI

10nm Gate-length junctionless gate-all-around (JL-GAA) FETs based 8T SRAM design under process variation using a cross-layer simulation

2014 SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)

2013 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)

2012 IEEE International SOI Conference (SOI)

IEEE 2011 International SOI Conference

2010 IEEE International SOI Conference (SOI)

2009 IEEE International SOI Conference

2008 IEEE International SOI Conference

2007 IEEE International SOI Conference

2006 IEEE international SOI Conferencee Proceedings

2005 IEEE International SOI Conference Proceedings

2004 IEEE International SOI Conference (IEEE Cat. No.04CH37573)

2003 IEEE International Conference on SOI

2002 IEEE International SOI Conference

2001 IEEE International SOI Conference. Proceedings (Cat. No.01CH37207)

2000 IEEE International SOI Conference. Proceedings (Cat. No.00CH37125)

1999 IEEE International SOI Conference. Proceedings (Cat. No.99CH36345)

1998 IEEE International SOI Conference Proceedings (Cat No.98CH36199)

1997 IEEE International SOI Conference Proceedings

1996 IEEE International SOI Conference Proceedings

1995 IEEE International SOI Conference Proceedings

Proceedings. IEEE International SOI Conference

Proceedings of 1993 IEEE International SOI Conference

1992 IEEE International SOI Conference

1991 IEEE International SOI Conference Proceedings

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4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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