NDLI: A synchronous interface for SoCs with multiple clock domains

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IEEE International SOC Conference, 2004. Proceedings.

Proceedings. IEEE International SOC Conference (IEEE Cat. No.04TH8744)

Proceedings - IEEE International SOC Conference [2004] - Title

Message from the General Chair

Message From the Technical Program Chair

Program-At-A Glance

2004 SOCC Organizing Committee / 2004 SOCC Steering Committee

Technical Program Commiftee

List of reviewers

Table of contents

Session quick index

Session MA1: Reconfigurable Applications

Fast parallel soft Viterbi decoder mapping on a reconfigurable DSP platform

Video transmission through domain specific reconfigurable architecurtes over short distance wireless medium utilizing Bluetooth IEEE 802.15.1/spl trade/ standard [architecurtes read architectures]

Session MB1: On-Chip Testing of Embedded Silicon Transducers

On-chip testing of embedded silicon transducers

Session MC1: Multi-Threshold Circuits

Fast techniques for standby leakage reduction in MTCMOS circuits

Analysis and design of low-power multi-threshold MCML

Session MA2: Analog to Digital Conversion

A high-speed power and resolution adaptive flash analog-to-digital converter

A background calibration scheme for pipelined ADCs including non-linear operational amplifier gain and reference error correction

Analog-to-digital conversion for SONET OC-192

Parallel time interleaved delta sigma band pass analog to digital converter for SOC applications

Session MB2: System Level Architecture and Design

Transparent SOC: on-chip analyzing techniques and implementation for embedded processor

A circuit-switched network architecture for network-on-chip

Clock tree tuning using shortest paths polygon

Multilevel routing with jumper insertion for antenna avoidance

Session MC2: Deep-Submicron Design

Signal integrity implications of inductor-to-circuit proximity

POMR: a power-optimal maze routing methodology

Coaxial polymer pillars: ultra-low inductance compliant wafer-level electrical input/output interconnects for power distribution

Leakage aware SER reduction technique for UDSM logic circuits

Session MA3: RF Circuits

A generic macromodel for coupling between inductors and interconnects for R.F.I.C. layouts

3-22GHz CMOS distributed single-balanced mixer

Impact of technology scaling on RF CMOS

Session MB3: Design and Analysis Tools

Silencer!: a tool for substrate noise coupling analysis

Adaptive response surface modeling-based method for analog circuit sizing

Circuit level modeling and simulation of mixed-technology systems

Session MC3: Low Power Signal Processing

Power-efficient implementation of turbo decoder in SDR system

A power-aware scalable pipelined Booth multiplier

High throughput and low power FIR filtering IP cores

Synthesis of SystemC models from SDF Ptolemy descriptions

A scalable and robust rail-to-rail delay cell for DLLs

FPGA implementation of efficient Kalman band-pass sigma-delta filter for application in FM demodulation

System-level design of low-cost FPGA hardware for real-time ICA-based blind source separation

A 0.13/spl mu/m 1Gb/s/channel store-and-forward network on-chip

A memory allocation and assignment method using multiway partitioning

Low-power driven standard-cell placement based on a multilevel force-directed algorithm

Mixed-signal DFE for multi-drop, gb/s, memory buses - a feasibility study

Bandgap yield loss due to dislocations on RFSiGe transceiver ICs: failure analysis, design

A novel phase detector for PAM-4 clock recovery in high speed serial links

An efficient reformulation based architecture for adaptive forward error correction decoding in wireless applications

A new level shifter in ultra deep sub-micron for low to wide range voltage applications

Design of a programmable cryptoprocessor for multiple cryptosystems

Exploration of GFP frame delineation architectures for network processing

Reducing crosstalk noise in high speed FPGAs

Coarse-grain reconfigurable XPP devices for adaptive high-end mobile video-processing

Robust multi-phase clock generation with reduced jitter

A low clock load conditional flip-flop

Crosstalk induced fault analysis in DRAMs

A synchronous interface for SoCs with multiple clock domains

Achieving higher dynamic range in flash A/D converters

Low energy transmission coding for on-chip serial communications

Clock tree layout design for reduced delay uncertainty

Session TA1: Embedded Processors for SOC

A 800 MHz PowerPC SOC with PCI-X DDR266, DDRII-667, and RAID assist

An embedded read only memory architecture with a complementary and two interchangeable power/performance design points

A generic reconfigurable neural network architecture as a network on chip

Application specific instruction memory transformations for power efficient, fault resilient embedded processors

Session TB1: High Performance Systems and Architectures

Multi-processor SoC integration: a case study on BlueGene/L

Communication on a segmented bus

High speed mixed analog/digital PRML architecture for optical data storage system

A high-performance parallel mode EBCOT encoder architecture design for JPEG2000

Session TA2: Design for Testability and Reliability

SRAM word-oriented redundancy methodology using built in self-repair

On-chip network based embedded core testing

An efficient error-masking technique for improving the soft-error robustness of static CMOS circuits

Session TB2: Low Power Design

Low-power on-chip bus architecture using dynamic relative delays

Battery-efficient task execution on portable reconfigurable computing

A leakage-tolerant low-leakage register file with conditional sleep transistor

Session TA3: High Performance Circuits and Methodologies

MOS current mode logic: design, optimization, and variability

A 32Kb SRAM cache using current mode operation and asynchronous wave-pipelined decoders

Simultaneous bidirectional PAM-4 link with built-in self-test

Retiming and clock scheduling to minimize simultaneous switching

Session TB3: Network Processing Architectures and Circuits

Network processors for access network (NP4AN): trends and challenges

A weighted fair queuing finishing tag computation architecture and implementation

An asynchronous on-chip network router with quality-of-service (QoS) support

Session TA4: Reconfigurable Architectures

An optically differential reconfigurable gate array using a 0.18 /spl mu/m CMOS process

Rapid energy estimation of computations on FPGA based soft processors

A virtual channel router for on-chip networks

Session TB4: Various Issues of SOC

An adaptive 4-PAM decision-feedback equalizer for chip-to-chip signaling

Substrate noise optimization in early floorplanning for mixed signal SOCs

A new multi-channel on-chip-bus architecture for system-on-chips

Session WA1: Analog Circuits I

Analysis and design of monolithic, high PSR, linear regulators for SoC applications

High-gain high-speed operational amplifier in digital 120nm CMOS

A compensation technique for transistor mismatch in current mirrors

A new design for built-in self-test of 5GHz low noise amplifiers

Session WB1: Interconnect Modeling

Decoupling capacitors for power distribution systems with multiple power supply voltages

Low power repeaters driving RC interconnects with delay and bandwidth constraints

Global interconnect optimization with simultaneous macrocell placement and repeater insertion

Mutual inductance modeling for multiple RLC interconnects with application to shield insertion

Session WA2: Wireless Communication

A novel half-rate architecture for high-speed clock and data recovery

SoC design of remote terminals for wireless telemetry system

An improved delay-hopped transmitted-reference ultra wideband architecture

Session WB2: Digital Signal Processing

VLSI design and analysis of a critical-band processor for speech recognition

An application-specific processor hard macro for real-time control

FPGA-efficient phase-to-I/Q architecture

Session WA3: Analog Circuits II

A 3.8Ghz channel-select filter using 0.18/spl mu/m CMOS

Optimum design and trade-offs for a triple-band LNA for GSM, WCDMA and GPS applications

Session WB3: Low Power Architecture

Extended dynamic voltage scaling for low power design

ChipPower: an architecture-level leakage simulator

CoolPression - a hybrid significance compression technique for reducing energy in caches

IEEE International [Systems-on-Chip] SOC Conference, 2003. Proceedings.

A synchronous interface for SoCs with multiple clock domains

Content Provider	IEEE Xplore Digital Library
Author	Sathe, V. Ziesler, C. Papaefihymiou, M. Kinfl, S. Kosonocky, S.
Copyright Year	2004
Description	Author affiliation: Dept. of EECS, Michigan Univ., Ann Arbor, MI, USA (Sathe, V.; Ziesler, C.; Papaefihymiou, M.)
Abstract	This paper presents an interface technique for hazard-free communication among synchronous intellectual property (IP) cores that belong to different clock domains. By allowing each IP core to run at its most efficient operating point, the proposed interface can yield significant power reductions in synchronous system-on-chip (SoC) designs. The technique is probably correct and achieves maximum throughput when transferring data across long distances. Its performance has been assessed through Hspice simulations.
Sponsorship	IEEE Circuits and Syst. Soc
Starting Page	173
Ending Page	174
File Size	158352
Page Count	2
File Format	PDF
ISBN	0780384458
DOI	10.1109/SOCC.2004.1362396
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2004-09-12
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Clocks Frequency synchronization Principal component analysis Throughput Delay lines Circuit optimization Digital circuits Intellectual property System-on-a-chip Power dissipation
Content Type	Text
Resource Type	Article

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