NDLI: Reconfigurable FPGA Implementation of Product Accumulate Codes

Content Provider	IEEE Xplore Digital Library
Author	Koh, Tiong Aik Ng, Boon Chong Guan, Yong Liang Li, Tiffany Jing
Copyright Year	2007
Description	Author affiliation: Department of ECE, Lehigh University, Bethlehem, PA 18015, USA (Li, Tiffany Jing) \|\| School of EEE, Nanyang Technological University, Singapore 639798, Singapore (Koh, Tiong Aik; Ng, Boon Chong; Guan, Yong Liang)
Abstract	A memory-based, pipelined, serial architecture is developed for implementing product accumulate codes in field programmable gate arrays. A three-stage pipeline structure is exploited on the min-sum decoding algorithm to achieve full utilization of instantiated resources, to reduce latency, and to increase throughput while keeping the performance degradation minimal. Different types of interleavers are investigated and the quadratic permutation polynomial based inter-leaver is shown to be the best choice in terms of implementation cost, reconfigurability and bit error rate performance. The proposed decoder implemented in Xilinx 2v3000FG676-4 chips is capable of processing one full decoding iteration for 1 encoded bit every clock. Thus regardless of the block size, throughput will be determined only by the number of iterations done while latency is linear to block size.
Starting Page	249
Ending Page	254
File Size	581512
Page Count	6
File Format	PDF
ISBN	9781424412211
ISSN	15206130
DOI	10.1109/SIPS.2007.4387553
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2007-10-17
Publisher Place	China
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Field programmable gate arrays Delay Throughput Iterative decoding Memory architecture Pipelines Degradation Polynomials Costs Bit error rate Prime Factor Interleaver Interleaver Reconfigurable Product Accumulate code FPGA
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Libarray of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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