NDLI: Reliable matching of 300 mm defect inspection tools @ sub 60 nm defect size

Content Provider	IEEE Xplore Digital Library
Author	Nutsch, A. Supplieth, F. Pfitzner, L. Ryssel, H.
Copyright Year	2005
Description	Author affiliation: Fraunhofer Inst. Integrated Syst. & Device Technol., Erlangen, Germany (Nutsch, A.; Supplieth, F.; Pfitzner, L.; Ryssel, H.)
Abstract	This paper describes advanced methodologies for defect inspection studies and tool matching at sub 60 nm defect size. The methodologies were affirmed by experimental results achieved on different defect inspection systems designed for non-patterned wafers. The defect inspection has been described successfully by the binomial distribution. The reliability of matching of defect inspection systems was improved by using defect maps. It is anticipated that the methodologies will be applicable for defect inspection of both, patterned and non patterned wafers.
Sponsorship	IEEE Electron Devices Soc. IEEE Components Packaging and Manuf. Technol. Soc., Semicond. Equip. & Mater. Int. (SEMI) Soc. of Appl. Phys. of Japan
Starting Page	245
Ending Page	248
File Size	290593
Page Count	4
File Format	PDF
ISBN	0780391438
DOI	10.1109/ISSM.2005.1513347
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2005-09-13
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Inspection Light scattering Particle scattering Silicon Detectors Nanoelectronics Semiconductor device manufacture Cleaning Equations Testing
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Libarray of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

FOUP cleaning - FOSB transportation: a challenge for manufacturing on 300 mm wafers

Light scattering by silicon wafer defects analysis based on discrete sources method

Resident-entity based simulation of batch chamber tools in 300 mm semiconductor manufacturing

High-resolution alpha-particle spectrometry using silicon carbide semiconductor detectors

300 mm wafer fabrication line simulation model

Prioritized automatic material handling services in 300 mm foundry manufacturing

Simulation of defect detection schemes for wafer inspection in VLSI manufacturing

Backside Wafer Damage Induced Wafer Front Side Defect and Yield Impact

300 mm megasonic cleaning process to address material consumption requirements for sub-65nm

Reliable matching of 300 mm defect inspection tools @ sub 60 nm defect size

Similar Documents

FOUP cleaning - FOSB transportation: a challenge for manufacturing on 300 mm wafers

Light scattering by silicon wafer defects analysis based on discrete sources method

Resident-entity based simulation of batch chamber tools in 300 mm semiconductor manufacturing

High-resolution alpha-particle spectrometry using silicon carbide semiconductor detectors

300 mm wafer fabrication line simulation model

Prioritized automatic material handling services in 300 mm foundry manufacturing

Simulation of defect detection schemes for wafer inspection in VLSI manufacturing

Backside Wafer Damage Induced Wafer Front Side Defect and Yield Impact

300 mm megasonic cleaning process to address material consumption requirements for sub-65nm

Reliable matching of 300 mm defect inspection tools @ sub 60 nm defect size