NDLI: A 24 GHz low power low phase noise dual-mode phase locked loop frequency synthesizer for 60 GHz applications

Content Provider	IEEE Xplore Digital Library
Author	Mahalingam, N. Yisheng Wang Kaixue Ma Kiat Seng Yeo Shou Xian Mou
Copyright Year	2014
Description	Author affiliation: Sch. of Electr. & Electron. Eng., Nanyang Technol. Univ., Singapore, Singapore (Mahalingam, N.; Yisheng Wang; Kaixue Ma; Kiat Seng Yeo; Shou Xian Mou)
Abstract	This paper presents a dual-mode PLL synthesizer used in 60 GHz transceiver supporting both IEEE 802.11ad and IEEE 802.15.3c standards with low power consumption and low phase noise. Fabricated in commercial 0.18 μm SiGe BiCMOS process and operated with a single 1.8 V supply, the PLL synthesizer provides output frequencies from 22.5 GHz to 26.23 GHz with phase noise better than -99.5 dBc/Hz at 1 MHz offset in both the integer and fractional modes of operation. The PLL synthesizer consumes low power of only 42 mW and occupies an area of 1.7 mm × 0.8 mm.
Sponsorship	IEEE Microwv. Theory Tech. Soc.
Starting Page	1
Ending Page	4
File Size	1629416
Page Count	4
File Format	PDF
ISBN	9781479938698
DOI	10.1109/MWSYM.2014.6848405
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2014-06-01
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Synthesizers Educational institutions Oscillators Coils Frequency modulation K-band phase locked loop (PLL) 24 GHz 60 GHz dual-mode frequency synthesizer fractional-N integer-N
Content Type	Text
Resource Type	Article

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A 24 GHz low power low phase noise dual-mode phase locked loop frequency synthesizer for 60 GHz applications