NDLI: FPGA design of a truncated SVD based receiver for the detection of SEFDM signals

Content Provider	IEEE Xplore Digital Library
Author	Grammenos, R.C. Isam, S. Darwazeh, I.
Copyright Year	2011
Description	Author affiliation: Department of Electronic and Electrical Engineering, University College London, WC1E 7JE, UK (Grammenos, R.C.; Isam, S.; Darwazeh, I.)
Abstract	This work presents the hardware design of a novel algorithm using Field Programmable Gate Arrays (FPGAs) for the detection of Spectrally Efficient Frequency Division Multiplexing (SEFDM) signals. Previous work has shown that a sub-optimal Truncated Singular Value Decomposition (TSVD) approach is well-suited for use in SEFDM systems. TSVD offers a targeted reduction in complexity while outperforming linear detectors, such as Zero Forcing (ZF) and Minimum Mean Squared Error (MMSE), in terms of Bit Error Rate (BER). This is the first time a hardware design for the TSVD algorithm has been devised for implementation on an FPGA device using Very high speed integrated circuit Hardware Description Language (VHDL). Results show excellent fixed-point performance which are comparable to existing floating-point computer-based simulations. The optimal parameters required to achieve this outcome combined with their effect on system performance are identified. The impact of finite FPGA resources against performance gain is also examined.
Starting Page	2085
Ending Page	2090
File Size	666559
Page Count	6
File Format	PDF
ISBN	9781457713460
e-ISBN	9781457713484
e-ISBN	9781457713477
DOI	10.1109/PIMRC.2011.6139882
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2011-09-11
Publisher Place	Canada
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Detectors Field programmable gate arrays Hardware Bit error rate Receivers Bandwidth Algorithm design and analysis implementation OFDM SEFDM FPGA VHDL spectral efficiency truncated singular value decomposition
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Mr. Siddhartha Mukherjee siddhartha@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	ndl-support@iitkgp.ac.in
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