NDLI: BTI and leakage aware dynamic voltage scaling for reliable low power cache memories

Content Provider	IEEE Xplore Digital Library
Author	Rossi, D. Tenentes, V. Khursheed, S. Al-Hashimi, B.M.
Copyright Year	2015
Description	Author affiliation: Electr. Eng. & Electron, Univ. of Liverpool, Liverpool, UK (Khursheed, S.) \|\| ECS, Univ. of Southampton, Southampton, UK (Rossi, D.; Tenentes, V.; Al-Hashimi, B.M.)
Abstract	We propose a novel dynamic voltage scaling (DVS) approach for reliable and energy efficient cache memories. First, we demonstrate that, as memories age, leakage power reduction techniques become more effective due to sub-threshold current reduction with aging. Then, we provide an analytical model and a design exploration framework to evaluate trade-offs between leakage power and reliability, and propose a BTI and leakage aware selection of the “drowsy” state retention voltage for DVS of cache memories. We propose three DVS policies, allowing us to achieve different power/reliability trade-offs. Through SPICE simulations, we show that a critical charge and a static noise margin increase up to 150% and 34.7%, respectively, is achieved compared to standard aging unaware drowsy technique, with a limited leakage power increase during the very early lifetime, and with leakage energy saving up to 37% in 10 years of operation. These improvements are attained at zero or negligible area cost.
Starting Page	194
Ending Page	199
File Size	19201154
Page Count	6
File Format	PDF
e-ISBN	9781467379052
DOI	10.1109/IOLTS.2015.7229858
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2015-07-06
Publisher Place	Greece
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Reliability Degradation Standards Voltage control Transistors Cache memory Aging
Content Type	Text
Resource Type	Article

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