NDLI: SEU-X: A SEu un-excitability prover for SRAM-FPGAs

Content Provider	IEEE Xplore Digital Library
Author	Bernardeschi, C. Cassano, L. Domenici, A.
Copyright Year	2012
Description	Author affiliation: Department of Information Engineering, University of Pisa, Italy (Bernardeschi, C.; Cassano, L.; Domenici, A.)
Abstract	We propose an un-excitability prover for Single Event Upset (SEU) faults affecting the configuration memory of logic resources of SRAM-FPGA systems. In particular, we focus on the subset of untestable faults that cannot even be excited, with the aim of optimizing the generation of test patterns, in particular for in-service testing. SEUs in configuration bits of the logic resources actually used by the system are addressed. This makes our fault model much more accurate than the classical stuck-at fault model. The tool relies on the SAL specification language for the modeling of netlists, and on the SAL model checker for the proof of the un-excitability of faults. Results from the application of the tool to some circuits from the ISCAS and ITC benchmarks are reported.
Starting Page	25
Ending Page	30
File Size	368626
Page Count	6
File Format	PDF
ISBN	9781467320825
e-ISBN	9781467320856
DOI	10.1109/IOLTS.2012.6313836
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2012-06-27
Publisher Place	Spain
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Circuit faults Table lookup Integrated circuit modeling Field programmable gate arrays Testing Safety Multiplexing Untestability Proof Model-Checking SAL Single Event Upset SRAM-FPGA
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Mr. Siddhartha Mukherjee siddhartha@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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Early assessment of SEU sensitivity through untestable fault identification

Experimental SEU Impact on Digital Design Implemented in FPGAs

Quantitative SEU Fault Evaluation for SRAM-Based FPGA Architectures and Synthesis Algorithms

Study of an Automated Precise SEU Fault Injection Technique

Failure probability of SRAM-FPGA systems with Stochastic Activity Networks

Improving Reliability of SRAM-Based FPGAs by Inserting Redundant Routing

A novel CLB architecture to detect and correct SEU in LUTs of SRAM-based FPGAs

Unexcitability analysis of SEus affecting the routing structure of SRAM-based FPGAs

Testing interconnects of dynamic reconfigurable FPGAs

SEU-X: A SEu un-excitability prover for SRAM-FPGAs

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SEU-X: A SEu un-excitability prover for SRAM-FPGAs