NDLI: On code coverage measurement for Verilog-A

Content Provider	IEEE Xplore Digital Library
Author	Yuan-Bin Sha Mu-Shun Lee Chien-Nan Jimmy Liu
Copyright Year	2004
Description	Author affiliation: Dept. of Electr. Eng., Nat. Central Univ., Chung-li, Taiwan (Yuan-Bin Sha; Mu-Shun Lee; Chien-Nan Jimmy Liu)
Abstract	In order to verify the integration of digital circuits and analog circuits in a SOC design, HDL-A languages are proposed to describe analog circuits such that they can be simulated together with the digital circuits described in HDL code. For digital circuits, coverage-driven approach has been widely used to verify the quality of HDL designs. However, for analog models, there are still no suitable solutions to gauge their quality. Therefore, in this paper, we will first discuss the feasibility and its meaning of applying some existing coverage metrics to Verilog-A code. We also propose a new coverage metric, frequency coverage, for checking the completeness of the frequency response in Verilog-A designs. Using this coverage metric as an assistant to existing code coverage metrics, we can have more confidence on the correctness of the Verilog-A descriptions at different situations.
Sponsorship	IEEE Comput. Soc. Test Technol. Tech. Council IEEE Comput. Soc. Design Autom. Tech. Comm
Starting Page	115
Ending Page	120
File Size	595582
Page Count	6
File Format	PDF
ISBN	0780387147
ISSN	15526674
DOI	10.1109/HLDVT.2004.1431251
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2004-11-10
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Hardware design languages Analog circuits Circuit simulation Digital circuits Computational modeling Frequency response Integrated circuit measurements Process design Testing Performance evaluation
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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