NDLI: FPGA implementation of a single-channel HDLC Layer-2 protocol transmitter using VHDL

Content Provider	IEEE Xplore Digital Library
Author	Qasim, S.M. Abbasi, S.A.
Copyright Year	2003
Description	Author affiliation: Dept. of Electr. Eng., King Saud Univ., Riyadh, Saudi Arabia (Qasim, S.M.; Abbasi, S.A.)
Abstract	To successfully transmit data over any network, a protocol is required to manage the flow or pace at which the data is transmitted. This protocol is defined in Layer 2 of OSI (Open Systems Interconnection) model. High-level Data Link Control (HDLC) is the most commonly used Layer 2 protocol and is suitable for bit oriented packet transmission mode. This paper discusses the VHDL modeling of single-channel HDLC Layer 2 protocol Transmitter and its implementation using Xilinx Virtex FPGA as the target technology. The HDLC Transmitter is used to transmit the HDLC frame structure. Implementing the single-channel HDLC protocol Transmitter in FPGA gives you the flexibility, upgradability and customization benefits of programmable logic.
Sponsorship	Telecom Egypt Mentor Graphics Egypt Nat. Telecommunications Inst. (NTI), Egypt Nat. Telecommunications Regulation Authority, (NTRA), Egypt Faculty of Eng., Cairo Univ., Egypt Academy of Scientific Res. and Technol., (ASRT), Egpyt MEMSCAP, Egypt High Technol. Center for Commun. and Elec., Faculty of Engin, Cairo Univ., Egypt Univ. of Waterloo, Canada IEEE Egpyt Section
Starting Page	265
Ending Page	268
File Size	266321
Page Count	4
File Format	PDF
ISBN	9770520101
DOI	10.1109/ICM.2003.237826
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2003-12-11
Publisher Place	Egypt
Access Restriction	Subscribed
Rights Holder	ECE-CUFE
Subject Keyword	Field programmable gate arrays Protocols Transmitters Cyclic redundancy check Registers Open systems Communication system control Programmable logic arrays Programmable logic devices ISO
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Mr. Siddhartha Mukherjee siddhartha@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	ndl-support@iitkgp.ac.in
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9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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