NDLI: McPAT: An integrated power, area, and timing modeling framework for multicore and manycore architectures

Content Provider	IEEE Xplore Digital Library
Author	Sheng Li Jung Ho Ahn Strong, R.D. Brockman, J.B. Tullsen, D.M. Jouppi, N.P.
Copyright Year	2009
Description	Author affiliation: University of Notre Dame, USA (Sheng Li; Brockman, J.B.) \|\| Seoul National University, Korea (Jung Ho Ahn) \|\| University of California, San Diego, USA (Strong, R.D.; Tullsen, D.M.) \|\| Hewlett-Packard Labs, USA (Jouppi, N.P.)
Abstract	This paper introduces McPAT, an integrated power, area, and timing modeling framework that supports comprehensive design space exploration for multicore and manycore processor configurations ranging from 90nm to 22nm and beyond. At the microarchitectural level, McPAT includes models for the fundamental components of a chip multiprocessor, including in-order and out-of-order processor cores, networks-on-chip, shared caches, integrated memory controllers, and multiple-domain clocking. At the circuit and technology levels, McPAT supports critical-path timing modeling, area modeling, and dynamic, short-circuit, and leakage power modeling for each of the device types forecast in the ITRS roadmap including bulk CMOS, SOI, and double-gate transistors. McPAT has a flexible XML interface to facilitate its use with many performance simulators. Combined with a performance simulator, McPAT enables architects to consistently quantify the cost of new ideas and assess tradeoffs of different architectures using new metrics like $energy-delay-area^{2}$ product $(EDA^{2}P)$ and energy-delay-area product (EDAP). This paper explores the interconnect options of future manycore processors by varying the degree of clustering over generations of process technologies. Clustering will bring interesting tradeoffs between area and performance because the interconnects needed to group cores into clusters incur area overhead, but many applications can make good use of them due to synergies of cache sharing. Combining power, area, and timing results of McPAT with performance simulation of PARSEC benchmarks at the 22nm technology node for both common in-order and out-of-order manycore designs shows that when die cost is not taken into account clustering 8 cores together gives the best energy-delay product, whereas when cost is taken into account configuring clusters with 4 cores gives the best $EDA^{2}P$ and EDAP.
Starting Page	469
Ending Page	480
File Size	1079632
Page Count	12
File Format	PDF
ISBN	9781605587981
ISSN	10724451
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2009-12-12
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Association for Computing Machinery, Inc. (ACM)
Subject Keyword	Timing Multicore processing Semiconductor device modeling Predictive models Costs Out of order Electronic design automation and methodology Integrated circuit interconnections Space exploration Microarchitecture Verification Performance
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
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3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Mr. Siddhartha Mukherjee siddhartha@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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