NDLI: Reducing power density through activity migration

Content Provider	IEEE Xplore Digital Library
Author	Seongmoo Heo Barr, K. Asanovic, K.
Copyright Year	2003
Description	Author affiliation: Lab. for Comput. Sci., MIT, Cambridge, MA, USA (Seongmoo Heo; Barr, K.; Asanovic, K.)
Abstract	Power dissipation is unevenly distributed in modern microprocessors leading to localized hot spots with significantly greater die temperature than surrounding cooler regions. Excessive junction temperature reduces reliability and can lead to catastrophic failure. We examine the use of activity migration which reduces peak junction temperature by moving computation between multiple replicated units. Using a thermal model that includes the temperature dependence of leakage power, we show that sustainable power dissipation can be increased by nearly a factor of two for a given junction temperature limit. Alternatively, peak die temperature can be reduced by 12.4/spl deg/C at the same clock frequency. The model predicts that migration intervals of around 20-200 /spl mu/s are required to achieve the maximum sustainable power increase. We evaluate several different forms of replication and migration policy control.
Sponsorship	ACM SIGDA IEEE Circuits & Syst. Soc. IEEE Solid-State Circuits Soc. IEEE Electron Devices Soc
Starting Page	217
Ending Page	222
File Size	655888
Page Count	6
File Format	PDF
ISBN	158113682X
DOI	10.1109/LPE.2003.1231865
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2003-08-27
Publisher Place	South Korea
Access Restriction	Subscribed
Rights Holder	Association for Computing Machinery, Inc. (ACM)
Subject Keyword	Power dissipation Packaging Power system modeling Temperature dependence Integrated circuit modeling Microprocessors Integrated circuit reliability Permission Thermal management Laboratories
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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