NDLI: Session 9: Metallization

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2015 IEEE International Interconnect Technology Conference and 2015 IEEE Materials for Advanced Metallization Conference (IITC/MAM)

IEEE International Interconnect Technology Conference

2013 IEEE International Interconnect Technology Conference - IITC

2012 IEEE International Interconnect Technology Conference

2011 IEEE International Interconnect Technology Conference

2010 IEEE International Interconnect Technology Conference

2009 IEEE International Interconnect Technology Conference

2008 International Interconnect Technology Conference

2007 IEEE International Interconnect Technology Conferencee

2006 International Interconnect Technology Conference

Proceedings of the IEEE 2005 International Interconnect Technology Conference, 2005.

Proceedings of the 2005 International Interconnect Technology Conference

Proceedings of the IEEE 2005 International Interconnect Technology Conference (IEEE Cat. No. 05TH8780)

Welcome to IITC 2005

Program-at-a-glance

2005 IITC Organizing Committee - Executive Committee

2005 IITC Program Committee

Table of contents

Session quick index

Session 1: Plenary Session

Shifting challenges in the integrated interconnection systems

Session 2: Integration

Integration of a mechanically reliable 65-nm node technology for low-k and ULK interconnects with various substrate and package types

BEOL process integration technology for 45 nm node porous low-k/copper interconnects

BEOL process integration with Cu/SiCOH (k=2.8) low-k interconnects at 65 nm groundrules

Comprehensive process design for low-cost chip packaging with circuit-under-pad (CUP) structure in porous-SiOCH film

45 nm-node BEOL integration featuring porous-ultra-low-k/Cu multilevel interconnects

Session 3: Poster Session I

Interface engineering for highly-reliable 65 nm-node Cu/ULK (k=2.6) interconnect integration

Process development and integration of electroless cobalt cap with low k carbon doped oxide

Infrastructure for successful BEOL characterization and yield ramp at the 65 nm node and below

Low-damage damascene patterning of SiOC(H) low-k dielectrics

Barrier layer effects on electromigration reliability of Cu/low k interconnects

New stress voiding observations in Cu interconnects

Impact of Cu barrier dielectrics upon stress-induced voiding of dual-damascene copper interconnects

Effects of friction and loading parameters on four-point bend adhesion measurements of low-k thin film interconnect structures

UV-hardened high-modulus CVD-ULK material for 45-nm node Cu/low-k interconnects with homogeneous dielectric structures

Hybrid low-k/Cu dual damascene process for 45-32 nm technology node using self-assembled porous-silica ultra low-k films

Using a low-k material with k=2.5 formed by a novel quasi-porogen approach for 65 nm Cu/LK interconnects

Reliability and conduction mechanism study on organic ultra low-k (k=2.2) for 65/45 nm hybrid Cu damascene technology

Influence of the diffusion barriers on the dielectric reliability of ULK/Cu advanced interconnects

Cu/ULK (k=2.0) integration for 45 nm node and below using an improved hybrid material with conventional BEOL processing and a late porogen removal

Effects of elastic modulus on the fracture behavior of low-dielectric constant films

First-principle molecular model of PECVD SiOCH film for the mechanical and dielectric property investigation

Session 4: Interconnect Systems

Impact of interconnect technology scaling on SOC design methodologies

Optimization of signal propagation performances in interconnects of the 45 nm node by exhaustive analysis of the technological parameters impact

Minimizing energy-per-bit for on-board LC transmission lines

High transmission performance integrated antennas on SOI substrate for VLSI wireless interconnects

Session 5: Dielectrics I

Reliability challenges accompanied with interconnect downscaling and ultra low-k dielectrics

2-dimensional distribution of dielectric constants in patterned low-k structures by a nm-probe STEM/valence EELS (V-EELS) technique

High-performance AlO-laminated TaO MIM capacitors for RF-IC applications: effects of the AlO layer on electrical characteristics

Effect of ash process on leakage mechanism of Cu/ELK (k=2.5) interconnect for 65/45 nm generation

Session 6: Reliability

Behavior of vacancies in EP-Cu films by positron-annihilation lifetime spectroscopy and its impact on SIV phenomena

Design of ECP additive for 65 nm-node technology Cu BEOL reliability

Electromigration threshold in copper interconnects and consequences on lifetime extrapolations

New insight into stress induced voiding mechanism in Cu interconnects

Effect of CoWP cap thickness on via yield and reliability for Cu interconnects with CoWP-only cap process

Session 7: Poster Session II

Capacitive impacts of dummies on interconnect propagation performances for integrated circuits of the 65 nm node and below

Design rules for improving predictability of on-chip antenna characteristics in the presence of other metal structures

Influence of CMP process on defects in SiOC films and TDDB reliability

The enabling solution of Cu/low-k planarization technology

Characterization of flip chip microjoins up to 40 GHz using silicon carrier

Investigation of an advanced SiH/sub 4/ based self-aligned barrier process for Cu BEOL reliability performance improvement on industrial 110 nm technology

Extendibility of PVD barrier/seed for BEOL Cu metallization

Integration and reliability of a noble TiZr/TiZrN alloy barrier for Cu/low-k interconnects

Evaluation of adhesion and barrier properties for CVD-TaN on dual damascene copper interconnects

Copper-filled through wafer vias with very low inductance

Analysis of surface roughness scattering and its contribution to conductivity degradation in nanoscale interconnects

Novel selective sidewall airgap process [single damascene interconnects]

Vertically aligned carbon nanofiber arrays for on-chip interconnect applications

Impact of deep sub-ambient cooling on GSI interconnect performance

High-density probe substrate for testing optical interconnects

Focus error reduction by photo-resist planarization in via-first dual damascene process

Supercritical CO/sub 2/ clean with novel solution for 65 nm and beyond BEOL performance improvement

Session 8: Novel I

Low temperature interconnect technology using surface activated bonding (SAB) method

Dual damascene process for air-gap Cu interconnects using conventional CVD films as sacrificial layers

The impact of technology on power for high-speed electrical and optical interconnects

Wafer-level microfluidic cooling interconnects for GSI

Session 9: Metallization

Current and future challenges of DRAM metallization

Low resistive and highly reliable Cu dual-damascene interconnect technology using self-formed MnSi/sub x/O/sub y/ barrier layer

An analysis of the effect of wire resistance on circuit level performance at the 45-nm technology node

Chemical dry cleaning technology for reliable 65 nm CMOS contact to NiSi/sub x/

Impact of size effects on the resistivity of copper wires and consequently the design and performance of metal interconnect networks

Session 10: Planarization

Novel electro-chemical mechanical planarization using carbon polishing pad to achieve robust ultra low-k/Cu integration

Membrane-mediated electropolishing of damascene copper

Understanding CMP-induced delamination in ultra low-k/Cu integration

Effect of CMP downward pressure on nano-scale residual stresses in dielectric films with Cu interconnects assessed by cathodoluminescence spectroscopy

Session 11: Dielectrics II

Surface acoustic waves as a technique for in-line detection of processing damage to low-k dielectrics

Impacts of UV cure for reliable porous PECVD SiOC integration [IC interconnect applications]

Effect of porosity on reducing cohesive strength and accelerating crack growth in ultra low-k thin-films [IC interconnect applications]

New spin-on oxycarbosilane low-k dielectric materials with exceptional mechanical properties

Session 12: Novel II

Interconnects for nanoelectronics

Low-resistance multi-walled carbon nanotube vias with parallel channel conduction of inner shells [IC interconnect applications]

Silicon-based building blocks for VLSI on-chip optical interconnects

Air gap integration for the 45nm node and beyond

Proceedings of the IEEE 2004 International Interconnect Technology Conference (IEEE Cat. No.04TH8729)

Proceedings of the IEEE 2003 International Interconnect Technology Conference (Cat. No.03TH8695)

Proceedings of the IEEE 2002 International Interconnect Technology Conference (Cat. No.02EX519)

Proceedings of the IEEE 2001 International Interconnect Technology Conference (Cat. No.01EX461)

Proceedings of the IEEE 2000 International Interconnect Technology Conference (Cat. No.00EX407)

Proceedings of the IEEE 1999 International Interconnect Technology Conference (Cat. No.99EX247)

Proceedings of the IEEE 1998 International Interconnect Technology Conference (Cat. No.98EX102)

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