NDLI: Program-at-a-glance

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2015 IEEE International Interconnect Technology Conference and 2015 IEEE Materials for Advanced Metallization Conference (IITC/MAM)

IEEE International Interconnect Technology Conference

2013 IEEE International Interconnect Technology Conference - IITC

2012 IEEE International Interconnect Technology Conference

2011 IEEE International Interconnect Technology Conference

2010 IEEE International Interconnect Technology Conference

2009 IEEE International Interconnect Technology Conference

2008 International Interconnect Technology Conference

2007 IEEE International Interconnect Technology Conferencee

2006 International Interconnect Technology Conference

Proceedings of the IEEE 2005 International Interconnect Technology Conference, 2005.

Proceedings of the IEEE 2004 International Interconnect Technology Conference (IEEE Cat. No.04TH8729)

Proceedings of the IEEE 2004 International Interconnect Technology Conference (IEEE Cat. No.04TH8729)

Proceedings of the 2004 International Interconnect Technology Conference

Welcome to IITC 2004

Program-at-a-glance

2004 IITC program committee

Table of contents

Session quick index

Session 2 metailization

Copper metallization for advanced interconnects: the electrochemical revolution

Highly reliable PVD/ALD/PVD stacked barrier metal structure for 45-nm node copper dual-damascene interconnects

Characteristics of PAALD-TaN thin films derived from TAIMATA precursor for copper metallization

Comprehensive electromigration studies on dual-damascene Cu interconnects with ALD WC/sub x/N/sub y/ barriers

Integration and performances of an alternative approach using copper silicide as a self-aligned barrier for 45 nm technology node Cu interconnects

Session 3 poster session I

The effect of FSG stability at high temperature on stress-induced voiding in Cu dual-damascene interconnects

Numerical characterization of the stress induced voiding inside via of various Cu/low k interconnects

Suppression of Cu extrusion into porous-MSQ film during chip-reliability test

TDDB degradation analysis using Ea of leakage current for reliable porous CVD SiOC(k=2.45)/Cu interconnects

Direct deposition of Cu/barrier stacks on dielectric/nonconductive layers using supercritical CO/sub 2/

A robust, deep-submicron copper interconnect structure using self-aligned metal capping method

Pore-sealing by etch-byproduct followed by ALD-Ta adhesion layer for Cu/porous low-k interconnects

Low damage via formation with low resistance by NH3 thermal reduction for Cu/ultra low-k interconnects

Influence of copper purity on microstructure and electromigration

Copper grain growth in reduced dimensions

Aluminum nano interconnects

Optimization of SiCOH dielectrics for integration in a 90nm CMOS technology

Highly manufacturable Cu/low-k dual damascene process integration for 65nm technology node

300mm copper low-k integration and reliability for 90 and 65 nm nodes

PECVD low-k SiOC (k=2.8) as a cap layer for 200nm pitch Cu interconnect using porous low-k dielectrics (k=2.3)

Session 4 reliability

Experiments and models for circuit-level assessment of the reliability of Cu metallization

High performance Cu interconnects capped with full-coverage ALD TaNx layer for Cu/low-k (k/spl sim/2.5) metallization

High reliability Cu interconnection utilizing a low contamination CoWP capping layer

Effects of dielectric liners on TDDB lifetime of a Cu/ low-k interconnect

Reliability of air-gap Cu interconnect and approach to selective W sealing using 90nm node technology

Session 5 process control, modeling

Direct observation of vacancy defects in electroplated Cu films

Quantitative control of plasma-surface interactions for highly reliable interconnects

Channel cracking in low-k films on patterned multi-layers

Session 6 packaging

Optimal implementation of sea of leads (SoL) compliant interconnect technology

Back-end compatibility of bonding and thinning processes for a wafer-level 3D interconnect technology platform

Extending on-die wiring hierarchy with wafer level packaging concepts

Chip-to-package interaction for a 90 nm Cu / PECVD low-k technology

Session 7 interconnect systems I

A model for power-supply noise injection in long interconnects

Power comparison between high-speed electrical and optical interconnects for inter-chip communication

Inductance enhancement in global clock distribution networks

High speed Si-based optical modulator for on-chip optical interconnects

Session 8 poster session II

Electrochemically induced defects during post Cu CMP cleaning

Enhancement in electrical via-yield of porous low-k/Cu integration by reducing CMP pressure

Measuring the elastic modulus and ultimate strength of low-k dielectric materials by means of the bulge test

X-ray and neutron porosimetry as powerful methodologies for determining structural characteristics of porous low-k thin films

Effect of bridging groups of precursors on modulus improvement in plasma co-polymerized low-k films

Film properties and integration performance of a nano-porous carbon doped oxide

Spin-on dielectric stack low-k integration with EB curing technology for 45nm-node and beyond

Effect of pore sealing on the reliability of ULK/Cu interconnects

Air gap technology by selective ozone/TEOS deposition

Ash-induced modification of porous and dense SiCOH inter-level-dielectric (ILD) materials during damascene plasma processing

An upper limit for aggregate I/O interconnect bandwidth of GSI chips constrained by power dissipation

A technique for incorporation of a heatsink for a system utilizing integrated circuits with wireless connections to an off-chip antenna

General compact model for bit-rate limit of electrical interconnects considering DC resistance, skin effect and surface scattering

On wafer de-embedding for SiGe/BiCMOS/RFCMOS transmission line interconnect characterization

Two-material, air-clad, grating-in-the-waveguide optical interconnects

Session 9 dielectrics I

Robust multilevel interconnects with a nano-clustering porous low-k (k<2.3)

3-dimensional structures of pores in low-k films observed by quantitative TEM tomograph and their impacts on penetration phenomena

Robust low-k film (k=2.1/spl sim/2.5) for 90/65 nm BEOL technology using bilayer film schemes

Session 10 etching, stripping, cleaning

Challenges of clean/strip processing for Cu/low-k technology

A charge damage study using an electron beam low k treatment

Ultra low-k integration solutions using GCIB processing

Session 11 process integration

BEOL process integration of 65nm Cu/low k interconnects

Process optimisation and dual damascene integration of porous CVD SiOC dielectric at 2.4 and 2.2 k-values for 45 nm CMOS technology

A 90nm high volume manufacturing logic technology featuring Cu metallization and CDO low-k ILD interconnects on 300 mm wafers

Cu/ULK integration using a post integration porogen removal approach

"Sea of Kelvin" multiple-pattern arrangement interconnect characterization for low-k/Cu dual damascene and its findings

Reliability, yield, and performance of a 90 nm SOI/Cu/SiCOH technology

Session 12 dielectrics II

Material issues for nanoporous ultra low-k dielectrics

The application of simultaneous ebeam cure methods for 65 nm node Cu/low-k technology with hybrid (PAE/MSX) structure

Novel molecular-structure design for PECVD porous SiOCH films toward 45nm node, ASICs with k=2.3

A plasma damage resistant ultra low-k hybrid dielectric structure for 45nm node copper dual-damascene interconnects

Session 13 planarization

Integrated electro-chemical mechanical planarization (Ecmp) for future generation device technology

Accelerated crack growth of nanoporous low-k glasses in CMP slurry environments

Characterization of patterned low-k film delamination during CMP for the 32nm node Cu/ultra low-k (k=1.6-1.8) integration

Session 14 interconnect systems II

Vertically-stacked on-chip SiGe/BiCMOS/RFCMOS coplanar waveguides

Intrachip optical interconnect: an above IC approach

Carbon nanotube vias for future LSI interconnects

Proceedings of the IEEE 2003 International Interconnect Technology Conference (Cat. No.03TH8695)

Proceedings of the IEEE 2002 International Interconnect Technology Conference (Cat. No.02EX519)

Proceedings of the IEEE 2001 International Interconnect Technology Conference (Cat. No.01EX461)

Proceedings of the IEEE 2000 International Interconnect Technology Conference (Cat. No.00EX407)

Proceedings of the IEEE 1999 International Interconnect Technology Conference (Cat. No.99EX247)

Proceedings of the IEEE 1998 International Interconnect Technology Conference (Cat. No.98EX102)

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4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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