NDLI: Micro power CMOS analog cells

Content Provider	IEEE Xplore Digital Library
Author	Salazar, F.A. Pimentel, J.C.G. Pacheco, M.A. Vellasco, M.
Copyright Year	1998
Description	Author affiliation: COPPE, Univ. Fed. do Rio de Janeiro, Brazil (Salazar, F.A.)
Abstract	Low power supply consumption has become one of the main issue in electronic industry for many product areas such as cellular telephones, portable personal computers and biomedical implants. The aim of this work is to investigate the main drawbacks involved in the design of CMOS analog cells biased in weak inversion. Biasing a cell in weak inversion makes it possible to achieve a power consumption that is one thousandth lower than common analog cells designed to operate in strong inversion. This work has involved the following subjects: a study of models for MOS transistors operating in weak inversion and strong inversion regions; a methodology to convert LEVEL 2 Spice model to EKV model; study of basic analog cell blocks suitable for low power mixed-mode IC design; design methodology for low power analog cells; comparison between these cells and some commercial ones; study of analog layout techniques.
Starting Page	187
Ending Page	190
File Size	38491
Page Count	4
File Format	PDF
ISBN	0818687045
DOI	10.1109/SBCCI.1998.715438
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1998-10-03
Publisher Place	Brazil
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Integrated circuit modeling Design methodology Electronics industry Telephony Microcomputers Implants Energy consumption Semiconductor device modeling MOSFETs Analog integrated circuits
Content Type	Text
Resource Type	Article

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4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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