NDLI: Possibilities and limitations of I/sub DDQ/ testing in submicron CMOS

Content Provider	IEEE Xplore Digital Library
Author	Figueras, J.
Copyright Year	1997
Description	Author affiliation: Dept. d'Enginyeria Electronica, Univ. Politecnica de Catalunya, Barcelona, Spain (Figueras, J.)
Abstract	I/sub DDQ/ testing is a well accepted testing approach based on the observation of the quiescent current consumption. Its growing industrial implementation is based on the possibility of detecting defects which scope other more traditional testing methods. However, its application costs are higher and its effectiveness in deep submicron technologies may decrease if the current trend of leakage increase is not stopped by creative innovation.
Starting Page	174
Ending Page	185
File Size	577714
Page Count	12
File Format	PDF
ISBN	0780342763
ISSN	10947116
DOI	10.1109/ICISS.1997.630258
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1997-10-08
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Circuit testing CMOS technology Logic testing Costs Integrated circuit testing Technological innovation CMOS process Histograms Circuit faults Manufacturing
Content Type	Text
Resource Type	Article

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Possibilities and limitations of I/sub DDQ/ testing in submicron CMOS