NDLI: A VLSI inner product macrocell

Content Provider	IEEE Xplore Digital Library
Author	Breveglieri, L. Dadda, L.
Copyright Year	1996
Description	Author affiliation: Dipartimento di Elettronica e Inf., Politecnico di Milano, Italy (Breveglieri, L.)
Abstract	Microcontrollers for embedded computer applications require a library of dedicated macrocells for specific applications. Arithmetic and basic DSP computations may be too inefficient when computed by software on the core CPU of the microcontroller. The architecture of a VLSI macrocell, for the ST9 microcontroller (8 bit), dedicated to the computation of the inner (scalar) product of two vectors of integer numbers and based on the multiply and accumulate algorithm, is here defined and developed. The arithmetic core of the macrocell is an integer pipeline. This macrocell fully interfaces to the ST9 environment and is optimised so as to achieve the maximum performances compatible with the bandwidth of the bus of ST9 and the minimum consumption of silicon area. The macrocell is implemented in CMOSM5H technology (0.7 /spl mu/ channel width) and its performances, measured in terms of silicon area and throughput, are evaluated.
Starting Page	26
Ending Page	35
File Size	613631
Page Count	10
File Format	PDF
ISBN	0780336399
ISSN	10632204
DOI	10.1109/ICISS.1996.552408
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1996-10-09
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Very large scale integration Macrocell networks Microcontrollers Arithmetic Silicon Computer applications Software libraries Application software Digital signal processing Computer architecture
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Libarray of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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