NDLI: Table of contents

Please wait, while we are loading the content...

2015 International Conference on Field Programmable Technology (FPT)

2013 International Conference on Field-Programmable Technology (FPT)

2012 International Conference on Field-Programmable Technology

2011 International Conference on Field-Programmable Technology

2010 International Conference on Field-Programmable Technology

2009 International Conference on Field-Programmable Technology

2008 International Conference on Field-Programmable Technology

2007 International Conference on Field-Programmable Technology

Proceedings 2007 International Conference on Field Programmable Technology

Message from the General Chair

Message from the Technical Program Co-chairs

Additional reviewers

Power and the Future FPGA Architectures

GRAPE-DR Project: a combination of peta-scale computing and high-speed networking

Table of contents

Memory Footprint Reduction for FPGA Routing Algorithms

SOC implementation of wave-pipelined circuits

Self-characterization of Combinatorial Circuit Delays in FPGAs

FPGA Cluster Computing in the ETA Radio Telescope

FPGA-based Accelerator Design for RankBoost in Web Search Engines

Asymmetric Multi-Processor Architecture for Reconfigurable System-on-Chip and Operating System Abstractions

Design and Implementation of an FPGA Architecture for High-Speed Network Feature Extraction

Architecting Hard Crossbars on FPGAs and Increasing their Area Efficiency with Shadow Clusters

A Method and FPGA Architecture for Real-Time Polymorphic Reconfiguration

Reconfigurable Functional Units for Scientific Superscalar Processors

A Coarse Grained Reconfigurable Architecture for Variable Block Size Motion Estimation

Instrumented Multi-Stage Word-Length Optimization

A Domain Specific Language for Reconfigurable Path-based Monte Carlo Simulations

Fused-Arithmetic Unit Generation for Reconfigurable Devices using Common Subgraph Extraction

Unifying FPGA Hardware Development

Applying Cuckoo Hashing for FPGA-based Pattern Matching in NIDS/NIPS

High Performance Hardware Implementation of SpikeProp Learning: Potential and Tradeoffs

The Image Forest Transform Architecture

A Highly Parallel FPGA based IEEE-754 Compliant Double-Precision Binary Floating-Point Multiplication Algorithm

TAS-MRAM based Non-volatile FPGA logic circuit

Bitstream Decompression for High Speed FPGA Configuration from Slow Memories

Dynamic Intellectual Property Protection for Reconfigurable Devices

Hardware/Software Co-design of a General-Purpose Computation Platform in Particle Physics

Efficient and High-Throughput Implementations of AES-GCM on FPGAs

A Framework for Implementing a Network-Based Stochastic Biochemical Simulator on an FPGA

An Approach for Applying Large Filters on Large Images using FPGA

Run-Time Management of Reconfigurable Hardware Tasks Using Embedded Linux

Implementations of Reconfigurable Logic Arrays on FPGAs

Net Length based Routability Driven Packing

FPGA-based Streaming Computation for Lattice Boltzmann Method

Reconfigurable Hardware Module Sequencer - A Tradeoff Between Networked and Data Flow Architectures

An Embedded Reconfigurable Logic Core based on Variable Grain Logic Cell Architecture

Improving Bounds for FPGA Logic Minimization

Floating-Point Matrix Multiplication in a Polymorphic Processor

A Secure Digital Content Delivery System Based on Partially Reconfigurable Hardware

Productivity of High-Level Languages on Reconfigurable Computers: An HPC Perspective

A Systolic Algorithm for the Quadratic Assignment Problem and its FPGA Implementation

Reconfiguration performance analysis of a dynamic optically reconfigurable gate array architecture

Efficient Mesh of Tree Interconnect for FPGA Architecture

Overwrite Configuration Technique in Multicast Configuration Scheme for Dynamically Reconfigurable Processor Arrays

An FPGA Based Travelling-Wave Fault Location System

NICFlex: A Functional Verification Accelerator for An RTL NIC Design

A Power Configurable Block Array Connected in Series as First Prototype Flex Power FPGA Chip

Optimal Buffering of FPGA Interconnect for Expected Delay Optimization

FPGA-Based 3-D engine for high-speed 3-D measurement based on light-section method

A 62.5 ns holographic reconfiguration of an optically differential reconfigurable gate array

Recursive Variable Expansion: A Loop Transformation for Reconfigurable Systems

A Rapid Prototyping of Real-Time Pattern Generator for Step-and-Scan Lithography Using Digital Micromirror Device

High Performance Software-Hardware Network Intrusion Detection System

A Domain-Specific Dynamically Reconfigurable Hardware Platform for Wireless Sensor Networks

FPGA Implementation of a Statically Reconfigurable Java Environment for Embedded Systems

A Dynamically Reconfigurable Architecture Combining Pixel-Level SIMD and Operation-Pipeline Modes for High Frame Rate Visual Processing

A Balanced Vector-Quantization Processor Eliminating Redundant Calculation for Real-Time Motion Picture Compression

Real-Time Segmentation of Color Images based on the K-means Clustering on FPGA

A Portable Memory Access Framework on Reconfigurable Computers

The Spiral Search: A Linear Complexity Algorithm for the Generation of Convex MIMO Instruction-Set Extensions

A Case for Soft Vector Processors in FPGAs

A Portable Co-Verification System Which Generates Testbench Automatically

Multiply Accumulate Unit Optimised for Fast Dot-Product Evaluation

A Novel Network Architecture Support for Fast Reconfiguration

A Mapping Method for Multi-Process Execution on Dynamically Reconfigurable Processors

A Programmable Load/Store Unit on C-based Hardware Design for FPGA

An efficient FPGA-based implementation of Pollard's (ρ - 1) factorization algorithm

A Novel Asynchronous e-FPGA Architecture for Security Applications

A Multiprocessor System-on-Chip Implementation of a Laser-based Transparency Meter on an FPGA

Compound Uniform Random Number Generators with On-Chhip Correlation and Distribution Measurements

Exploiting Slack Time in Dynamically Reconfigurable Processor Architectures

2006 IEEE International Conference on Field Programmable Technology

Proceedings. 2005 IEEE International Conference on Field-Programmable Technology, 2005.

Proceedings. 2004 IEEE International Conference on Field- Programmable Technology (IEEE Cat. No.04EX921)

Proceedings. 2003 IEEE International Conference on Field-Programmable Technology (FPT) (IEEE Cat. No.03EX798)

2002 IEEE International Conference on Field-Programmable Technology, 2002. (FPT). Proceedings.

Central Library (ISO-9001:2015 Certified)
Indian Institute of Technology Kharagpur
Kharagpur, West Bengal, India | PIN - 721302

See location in the Map
03222 282435
Mail: support@ndl.gov.in

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Libarray of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in