NDLI: Exploiting Modified Placement and Hardwired Resources to Provide High Reliability in FPGAs

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2015 IEEE 23rd Annual International Symposium on Field-Programmable Custom Computing Machines

2014 IEEE 22nd Annual International Symposium on Field-Programmable Custom Computing Machines

2013 IEEE 21st Annual International Symposium on Field-Programmable Custom Computing Machines

2012 IEEE 20th International Symposium on Field-Programmable Custom Computing Machines

Table of contents

A Message from the General Chair and Program Chair

Program Committee

Additional reviewers

Workshop description

A Low-Overhead Profiling and Visualization Framework for Hybrid Transactional Memory

Towards a Universal FPGA Matrix-Vector Multiplication Architecture

Impact of Cache Architecture and Interface on Performance and Area of FPGA-Based Processor/Parallel-Accelerator Systems

Area-Efficient Architectures for Large Integer and Quadruple Precision Floating Point Multipliers

Multi-Resolution Real-Time Dense Stereo Vision Processing in FPGA

A Mixed Precision Methodology for Mathematical Optimisation

Go Ahead: A Partial Reconfiguration Framework

On-the-fly Composition of FPGA-Based SQL Query Accelerators Using a Partially Reconfigurable Module Library

Fixed Point Lanczos: Sustaining TFLOP-equivalent Performance in FPGAs for Scientific Computing

Formic: Cost-efficient and Scalable Prototyping of Manycore Architectures

Fast Multi-Objective Algorithmic Design Co-Exploration for FPGA-based Accelerators

FLEXDET: Flexible, Efficient Multi-Mode MIMO Detection Using Reconfigurable ASIP

FX-SCORE: A Framework for Fixed-Point Compilation of SPICE Device Models Using Gappa++

FPGA-based Acceleration for Tracking Audio Effects in Movies

ZUMA: An Open FPGA Overlay Architecture

Efficient Query Processing for Web Search Engine with FPGAs

Power Management Strategies for Serial RapidIO Endpoints in FPGAs

Online Measurement of Timing in Circuits: For Health Monitoring and Dynamic Voltage & Frequency Scaling

An Extensible and Portable Tool Suite for Managing Multi-Node FPGA Systems

Remote Execution in Distributed Memory MPSoC

A Heterogeneous Architecture for Evaluating Real-Time One-Dimensional Computational Fluid Dynamics on FPGAs

Bluehive - A field-programable custom computing machine for extreme-scale real-time neural network simulation

Emulating Mammalian Vision on Reconfigurable Hardware

Exploiting Modified Placement and Hardwired Resources to Provide High Reliability in FPGAs

A Custom Precision Based Architecture for Accelerating Parallel Tempering MCMC on FPGAs without Introducing Sampling Error

Exploiting Memory-Level Parallelism in Reconfigurable Accelerators

Hardware Acceleration of Short Read Mapping

Short-Read Mapping by a Systolic Custom FPGA Computation

FMSA: FPGA-Accelerated ClustalW-Based Multiple Sequence Alignment through Pipelined Prefiltering

Accelerating Millions of Short Reads Mapping on a Heterogeneous Architecture with FPGA Accelerator

Memory Bandwidth Efficient Two-Dimensional Fast Fourier Transform Algorithm and Implementation for Large Problem Sizes

Specifying Compiler Strategies for FPGA-based Systems

Bus-based MPSoC Security through Communication Protection: A Latency-efficient Alternative

PATS: A Performance Aware Task Scheduler for Runtime Reconfigurable Processors

RIFFA: A Reusable Integration Framework for FPGA Accelerators

Groundhog - A Serial ATA Host Bus Adapter (HBA) for FPGAs

Shortening Design Time through Multiplatform Simulations with a Portable OpenCL Golden-model: The LDPC Decoder Case

Accelerating a Random Forest Classifier: Multi-Core, GP-GPU, or FPGA?

Cognitive Radio Universal Software Hardware

Designing Flexible Reconfigurable Regions to Relocate Partial Bitstreams

EBRAM - Extending the BlockRAMs in FPGAs to Support Caches and Hash Tables in an Efficient Manner

Implementing Murf: Accelerating Large State Space Exploration on FPGAs

ScalaPipe: A Streaming Application Generator

VENICE: A Compact Vector Processor for FPGA Applications

2011 IEEE 19th Annual International Symposium on Field-Programmable Custom Computing Machines

2010 18th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines

2009 17th IEEE Symposium on Field Programmable Custom Computing Machines

2008 16th International Symposium on Field-Programmable Custom Computing Machines

15th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2007)

2006 14th Annual IEEE Symposium on Field-Programmable Custom Computing Machines

13th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM'05)

12th Annual IEEE Symposium on Field-Programmable Custom Computing Machines

11th Annual IEEE Symposium on Field-Programmable Custom Computing Machines, 2003. FCCM 2003.

Proceedings. 10th Annual IEEE Symposium on Field-Programmable Custom Computing Machines

The 9th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM'01)

Proceedings 2000 IEEE Symposium on Field-Programmable Custom Computing Machines (Cat. No.PR00871)

Seventh Annual IEEE Symposium on Field-Programmable Custom Computing Machines (Cat. No.PR00375)

Exploiting Modified Placement and Hardwired Resources to Provide High Reliability in FPGAs

Content Provider	IEEE Xplore Digital Library
Author	Nazar, G.L. Carro, L.
Copyright Year	2012
Abstract	Possible scenarios for future manufacturing technologies increase the desirable features of fault tolerance techniques, such as coping with multiple faults and reducing error latency. On the other hand, current high-end FPGAs present, besides lookup tables and flip-flops, several dedicated components that perform the most commonly required functions. In this paper, we propose an approach to use such resources to efficiently provide fault detection capabilities. We further extend the technique with placement constraints to enhance the detection of faults affecting the routing resources, which is a critical demand for such devices.
Starting Page	149
Ending Page	152
File Size	178745
Page Count	4
File Format	PDF
ISBN	9781467316057
DOI	10.1109/FCCM.2012.56
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2012-04-29
Publisher Place	Canada
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Table lookup Field programmable gate arrays Circuit faults Routing Delay Redundancy Reliable Routing Field Programmable Gate Array Concurrent Error Dection
Content Type	Text
Resource Type	Article

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