NDLI: A Task Graph Approach for Efficient Exploitation of Reconfiguration in Dynamically Reconfigurable Systems

Content Provider	IEEE Xplore Digital Library
Author	Papademetriou, K. Dollas, A.
Copyright Year	2006
Description	Author affiliation: Dept. of Electron. & Comput. Eng., Crete Tech. Univ., Chania (Papademetriou, K.; Dollas, A.)
Abstract	Partial reconfiguration suffers from the inherent high latency and low throughput which is more considerable when reconfiguration is performed on-demand. This work deals with this overhead in processors combining a fixed processing unit (FPU), and a reconfigurable processing unit (RPU). Static and dynamic prefetching (Li, 2002), and instruction forecasting (Iliopoulos and Antonakopoulos, 2001) are targeting at reduction of the overhead through preloading of configurations. Banerjee et al. (2005) transform the task graph of an application and a heuristic algorithm evaluates the reduction in schedule length and selects the most promising configuration. Tasks are scheduled according to the physical resource constraints. In this work the prefetching model of Li (2002) was augmented by taking into account the hardware area constraints of a partially reconfigurable system. Given the task graph of an application, tasks with low probability to be executed are split and preloaded according to the hardware in order to be fully utilized. Thus, the time during which reconfiguration is overlapped with processor execution is increased
Starting Page	307
Ending Page	308
File Size	107484
Page Count	2
File Format	PDF
ISBN	0769526616
DOI	10.1109/FCCM.2006.19
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2006-04-24
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Prefetching Delay Hardware High performance computing Throughput Heuristic algorithms Scheduling algorithm Testing
Content Type	Text
Resource Type	Article

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