NDLI: Design and analysis of a layer seven network processor accelerator using reconfigurable logic

Content Provider	IEEE Xplore Digital Library
Author	Memik, G. Memik, S.O. Mangione-Smith, W.H.
Copyright Year	2002
Description	Author affiliation: Dept. of Electr. Eng., California Univ., Los Angeles, CA, USA (Memik, G.)
Abstract	In this paper, we present an accelerator that is designed to improve performance of network processing applications, particularly layer seven networking applications. The accelerator can easily be integrated in Network Processors. We present the design details of two different FPGA implementations: a design where each task is implemented in the accelerator and another one where the accelerator must be partially reconfigured for different tasks. We also present novel algorithms for important tasks such as tree lookup and pattern matching that utilize the accelerator. We show that the accelerator improves the overall execution time by as much as 20-times for these tasks. We show that the accelerator can improve the execution time of a representative layer seven application by an order of magnitude. Finally, we discuss the effects of reconfiguration time and frequency over the performance of the accelerator.
Sponsorship	IEEE Comput. Soc. Tech. Committee on Comput. Architecture
Starting Page	131
Ending Page	140
File Size	459007
Page Count	10
File Format	PDF
ISBN	076951801X
DOI	10.1109/FPGA.2002.1106668
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2002-04-24
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Reconfigurable logic Application software Field programmable gate arrays Pattern matching Frequency Protocols Software performance Process design Algorithm design and analysis Computer science
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Mr. Siddhartha Mukherjee siddhartha@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	ndl-support@iitkgp.ac.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Libarray of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Reconfigurable parallel approximate string matching on FPGAs

Intelligent Reconfigurable Instruction Set Processor (IRISP) Design

Transformable computers

Design and analysis of a layer seven network processor accelerator using reconfigurable logic (2002).

Development and implementation of a Network Processor Architecture in reconfigurable logic (FPGA)

Delivering Acceleration: The Potential for Increased HPC Application Performance Using Reconfigurable Logic

A reconfigurable data path processor

Design and Analysis of a layer Seven Network Processor Accelerator Using Reconfigurable Logic (2002)

Field programmable gate array based reconfigurable preprocessor

Design and analysis of a layer seven network processor accelerator using reconfigurable logic

Similar Documents

Reconfigurable parallel approximate string matching on FPGAs

Intelligent Reconfigurable Instruction Set Processor (IRISP) Design

Transformable computers

Design and analysis of a layer seven network processor accelerator using reconfigurable logic (2002).

Development and implementation of a Network Processor Architecture in reconfigurable logic (FPGA)

Delivering Acceleration: The Potential for Increased HPC Application Performance Using Reconfigurable Logic

A reconfigurable data path processor

Design and Analysis of a layer Seven Network Processor Accelerator Using Reconfigurable Logic (2002)

Field programmable gate array based reconfigurable preprocessor

Design and analysis of a layer seven network processor accelerator using reconfigurable logic