NDLI: Design and implementation of a QoS router on FPGA

Content Provider	IEEE Xplore Digital Library
Author	Guohai Zheng Huaxi Gu Yintang Yang Keming Du Shilong Xu
Copyright Year	2011
Description	Author affiliation: School of Microelectronics, Xidian University, Xi'an, China (Yintang Yang) \|\| State Key Lab of ISN, Xidian University, Xi'an, China (Guohai Zheng; Huaxi Gu) \|\| The 54th Institute of CETC, Shijiazhuang, China (Keming Du; Shilong Xu)
Abstract	Router is the key unit of Network-on-Chip and there are many implementations of router for on chip network, but few of them provide QoS service. In this paper, we have exploited a QoS router based on a hybrid switching mechanism. By using the circuit-switching, the router can provide guaranteed services, at the same time it makes the most use of the remained network resources to provide best effort services with the wormhole-switching. What's more, to be able to implement it on chip lastly, we select the XC5VLX110T chip to establish a verification platform on RTL-level, also with some necessary analysis and verification. The synthesis of the router shows it consumes 1% of the chip's storage resources and 6% of the logic resources, and its maximum operating frequency is up to 155.441MHz when the width of the wire is set to be 8bit and the depth of buffer to be 16 flits.
Starting Page	1837
Ending Page	1840
File Size	1308598
Page Count	4
File Format	PDF
ISBN	9781457715860
e-ISBN	9781457715877
DOI	10.1109/ICCSNT.2011.6182327
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2011-12-24
Publisher Place	China
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	QoS FPGA Switches Network-on-Chip (NoC) Router Table lookup Registers Field programmable gate arrays Switching circuits
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Libarray of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Generic Low-Latency NoC Router Architecture for FPGA Computing Systems

Power optimization of LUT based FPGA circuits

Design and FPGA implementation of a QoS router for Networks-on-Chip

Homogeneous NoC-based FPGA: The Foundation for Virtual FPGA

Multi-FPGA implementation of a Network-on-Chip based many-core architecture with fast barrier synchronization mechanism

A flexible circuit switched NOC for FPGA based systems

A dependable and dynamic network on chip suitable for FPGA-based reconfigurable systems

Mathematical Models Applied to On-Chip Network on FPGA for Resource Estimation

Review of NoC-based FPGAs architectures

Design and implementation of a QoS router on FPGA

Similar Documents

Generic Low-Latency NoC Router Architecture for FPGA Computing Systems

Power optimization of LUT based FPGA circuits

Design and FPGA implementation of a QoS router for Networks-on-Chip

Homogeneous NoC-based FPGA: The Foundation for Virtual FPGA

Multi-FPGA implementation of a Network-on-Chip based many-core architecture with fast barrier synchronization mechanism

A flexible circuit switched NOC for FPGA based systems

A dependable and dynamic network on chip suitable for FPGA-based reconfigurable systems

Mathematical Models Applied to On-Chip Network on FPGA for Resource Estimation

Review of NoC-based FPGAs architectures

Design and implementation of a QoS router on FPGA