NDLI: Slew rate and delay optimization of sense amplifier using tradeoff between supply voltage and threshold

Content Provider	IEEE Xplore Digital Library
Author	Jain, G. Vyas, K. Maurya, V.K. Mehra, A.
Copyright Year	2014
Description	Author affiliation: ASET, Amity Univ., Noida, India (Mehra, A.) \|\| ECE Dept., GITS, Udaipur, India (Jain, G.; Vyas, K.; Maurya, V.K.)
Abstract	Output of SRAM memory circuit is very small i.e. in few milli volts. While reading logic 1 sometimes it is read as logic 0. Due to this malfunctioning of circuit, problem of hazards occur. To overcome this problem we use sense amplifiers. The work of sense amplifier is to sense low power signal from bit line of SRAM memory circuit and amplify the small voltage swing to recognizable logic levels so that data can be interpreted clearly by logic outside the memory. Here we have reduced the delay of the sense amplifier by optimizing the supply voltage i.e. VDD. For this purpose tradeoff between delays, VDD and offset voltage has been done. We have examined the results using IC flow tool.
Starting Page	1
Ending Page	5
File Size	463588
Page Count	5
File Format	PDF
ISBN	9781479973187
e-ISBN	9781479973194
DOI	10.1109/EIC.2015.7230745
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2014-08-10
Publisher Place	India
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Voltage measurement Sensitivity Noise Random access memory Threshold voltage Hazards Delays Transistors Sense Amplifier Offset voltage
Content Type	Text
Resource Type	Article

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Slew rate and delay optimization of sense amplifier using tradeoff between supply voltage and threshold