NDLI: Variability aware modeling of SEU induced failure probability of logic circuit paths in static conditions

Content Provider	IEEE Xplore Digital Library
Author	Khalid, U. Mastrandrea, A. Abbas, Z. Olivieri, M.
Copyright Year	2015
Description	Author affiliation: Dept. of Inf. Eng., Sapienza Univ. of Rome, Rome, Italy (Khalid, U.; Mastrandrea, A.; Abbas, Z.; Olivieri, M.)
Abstract	Voltage noise can lead to various errors such as dynamic and permanent, which are directly associated to circuit-level reliability issues. Variability in process parameters directly affects the probability of failures associated to voltage noise. Yet, the evaluation of the probability of failures by SPICE level Monte Carlo simulation is prohibitively time-consuming. This work proposes a technique to characterize the input noise and process variations in order to estimate failure probability in a logic circuit path composed of combinational cells and registers. The method allows to correctly estimate the order of magnitude of the probability of failures and to evidence the influence of process variations, while reaching $>10^{4}$ speedup versus SPICE.
Starting Page	1
Ending Page	4
File Size	247016
Page Count	4
File Format	PDF
e-ISBN	9781467372312
DOI	10.1109/ICRITO.2015.7359223
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2015-09-02
Publisher Place	India
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	CMOS Monte Carlo methods VLSI Logic gates SPICE Threshold voltage Process variations Registers Reliability Integrated circuit modeling
Content Type	Text
Resource Type	Article

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