NDLI: Flexible IP cores for the k-NN classification problem and their FPGA implementation

Content Provider	IEEE Xplore Digital Library
Author	Manolakos, E.S. Stamoulias, I.
Copyright Year	2010
Description	Author affiliation: Department of Informatics and Telecommunications, University of Athens, Panepistimioupolis, Ilisia, 15784, Greece (Manolakos, E.S.; Stamoulias, I.)
Abstract	The k-nearest neighbor (k-NN) is a popular non-parametric benchmark classification algorithm to which new classifiers are usually compared. It is used in numerous applications, some of which may involve thousands of data vectors in a possibly very high dimensional feature space. For real-time classification a hardware implementation of the algorithm can deliver high performance gains by exploiting parallel processing and block pipelining. We present two different linear array architectures that have been described as soft parameterized IP cores in VHDL. The IP cores are used to synthesize and evaluate a variety of array architectures for a different k-NN problem instances and Xilinx FPGAs. It is shown that we can solve efficiently, using a medium size FPGA device, very large size classification problems, with thousands of reference data vectors or vector dimensions, while achieving very high throughput. To the best of our knowledge, this is the first effort to design flexible IP cores for the FPGA implementation of the widely used k-NN classifier.
Starting Page	1
Ending Page	4
File Size	559125
Page Count	4
File Format	PDF
ISBN	9781424465330
e-ISBN	9781424465347
DOI	10.1109/IPDPSW.2010.5470733
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2010-04-19
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Multidimensional systems Parallel processing Throughput Vectors Hardware Classification algorithms Informatics Field programmable gate arrays Pipeline processing Nearest neighbor searches
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Mr. Siddhartha Mukherjee siddhartha@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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