NDLI: High performance pipelined architecture of Ghash

Content Provider	IEEE Xplore Digital Library
Author	Yan Bai Guochu Shou Yihong Hu Zhigang Guo
Copyright Year	2010
Description	Author affiliation: School of Information and Communication Engineering, Beijing University of Posts and Telecommunications, China (Yan Bai; Guochu Shou; Yihong Hu; Zhigang Guo)
Abstract	Ghash is the authentication function of GCM. In this paper, we propose a high performance pipelined architecture of Ghash. The pipelined architecture can boost the operating frequency of the hash function block that is the bottleneck for higher speed GCM hardware. The most attractive feature is our pipelined architecture based on divided-and-conquer algorithm. According to the architecture, the critical path of the multiply-adder used for Ghash is divided into 3-stage to obtain the higher throughput and reduce the time complexity. At the same, divided-and-conquer algorithm can efficiently reduce the space complexity. The proposed architecture is compared to previous work on resource consumption and throughput aspects, and evaluated by using Xilinx Virtex5. From the statistics of our analysis and implementation, the number of AND gates consumed reduces by 25%, the number of XOR gates consumed reduces by 21.4%, and the throughput increases by 12.556Gbps reaching to 43.32Gbps. This design makes it very easy to implement the low complexity and high speed architecture of Ghash, and the design adapts to high speed networks security for authentication function.
Starting Page	716
Ending Page	720
File Size	713084
Page Count	5
File Format	PDF
ISBN	9781424467693
e-ISBN	9781424467723
DOI	10.1109/ICBNMT.2010.5705183
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2010-10-26
Publisher Place	China
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Divided-and-Conquer Galois Field Radiation detectors Pipelined Authentication Logic gates Time frequency analysis Table lookup Cryptography Ghash Clocks
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Mr. Siddhartha Mukherjee siddhartha@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	ndl-support@iitkgp.ac.in
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7	National Digital Libarray of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
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9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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