NDLI: Computing in 3D

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2015 International 3D Systems Integration Conference (3DIC)

Conference schedule

3D system integration research at IMEC

Advanced 2.5D/3D hetero-integration technologies at GINTI, Tohoku University

3D research activities in ITRI

Current and future 3D activities at Fraunhofer

IME's capabilities and programs in 2.5D/3DIC

3D advanced integration technology for heterogeneous systems

Path to 3D heterogeneous integration

Invited talk: Some challenges in scaling 3D ICs to a broader application set

Reconfigured multichip-on-wafer (mCoW) Cu/oxide hybrid bonding technology for ultra-high density 3D integration using recessed oxide, thin glue adhesive, and thin metal capping layers

Intermediate BEOL process influence on power and performance for 3DVLSI

Silicon based dry-films evaluation for 2.5D and 3D Wafer-Level system integration improvement

Invited talk: Progress in 3D integrated circuits

Electrical performance of high bandwidth memory (HBM) interposer channel in terabyte/s bandwidth graphics module

New signal skew cancellation method for 2 Gbps transmission in glass and organic interposers to achieve 2.5D package employing next generation high bandwidth memory (HBM)

Novel local stress evaluation method in 3D IC using DRAM cell array with planar mOS capacitors

Characterization of stress distribution in ultra-thinned DRAM wafer

No pumping at 450°C with electrodeposited copper TSV

Thermal stability of electroplated copper thin-film interconnections

Invited talk: Technology and overview of Sony's 3D stacked CMOS image sensor

Three-dimensional integrated circuits and stacked CMOS image sensors using direct bonding of SOI layers

Fine-grained 3-D integrated circuit fabric using vertical nanowires

3D-IC technologies and 3D FPGA

The issues of automated driving vehicle and the expectations for 3D integration technology

Neuromorphic semiconductor memory

3D integration: Applications and market trends

Vacuum-assisted-spin-coating of polyimide liner for high-aspect-ratio TSVs applications

Nano-Function materials for TSV technologies

High-speed via hole filling using electrophoresis of Ag nanoparticles

Computing in 3D

Comprehensive comparison of 3D-TSV integrated solid-state drives (SSDs) with storage class memory and NAND flash memory

Power saving and noise reduction of 28nm CMOS RF system integration using integrated fan-out wafer level packaging (InFO-WLP) technology

3D ICs: An opportunity for fully-integrated, dense and efficient power supplies

New precision wafer bonding technologies for 3DIC

Permanent wafer bonding in the low temperature by using various plasma enhanced chemical vapour deposition dielectrics

High productivity thermal compression bonding for 3D-IC

Transfer and non-transfer stacking technologies based on chip-to-wafer self-asembly for high-throughput and high-precision alignment and microbump bonding

Mitigating thermo mechanical stress in high-density 3D-LSI through dielectric liners in Cu- through silicon Via _ µ-RS and µ-XRD study

TSV etching and VDP process integration for high reliability

Electrical investigation of Cu pumping in through-silicon vias for BEOL reliability in 3D integration

Long term efficacy of ultra-thin Ti passivation layer for achieving low temperature, low pressure Cu-Cu Wafer-on-Wafer bonding

Fast filling of through-silicon via (TSV) with conductive polymer/metal composites

Room-temperature bonding mechanism of compliant bump with ultrasonic assist

Influential factors in low-temperature direct bonding of silicon dioxide

Warpage analysis of organic substrates for 2.1D packaging

Guard-ring monitoring system for inspecting defects in TSV-based data buses

Electrical interconnect test method of 3D ICs by injected charge volume

Copper-filled anodized aluminum oxide a potential material for chip to chip bonding

Improved access pattern for ROB soft error rate mitigation based on 3D integration technology

Best engineering practice for thermal characterization of stacked dice FPGA devices

Electrical interconnect test of 3D ICs made of dies without ESD protection circuits with a built-in test circuit

Congestion-aware optimal techniques for assigning inter-tier signals to 3D-vias in a 3DIC

On TSV array defect detection method using two ring-oscillators considering signal transitions at adjacent TSVs

Crosstalk-included eye-diagram estimation for high-speed silicon, organic, and glass interposer channels on 2.5D/3D IC

Consideration of microbump layout for reduction of local bending stress due to CTE Mismatch in 3D IC

Characterization of the mechanical stress impact on device electrical performance in the CMOS and III–V HEMT/HBT heterogeneous integration environment

Design of a 3-D stacked floating-point Goldschmidt divider

Modeling and analysis of defects in through silicon via channel for non-invasive fault isolation

Development of high-quality low-temperature (≤ 120°C) PECVD-SiN films by organosilane

Investigation of effects of metalization on heat spreading in bump-bonded 3D systems

Enabling automatic system design optimization through Assembly Design Kits

Cost modeling and analysis for the design, manufacturing and test of 3D-ICs

Proposed static timing analysis framework for extracted 3D integrated circuits (3D-STA)

Noise coupling modeling and analysis of through glass via(TGV)

TSV noise coupling in 3D IC using guard ring

Power tile optimization and packaging for efficient temperature management of ASIC's in networking applications

Vertical integration after stacking (ViaS) process for low-cost and low-stress 3D silicon integration

All-wet TSV filling with highly adhesive displacement plated Cu seed layer

Variation of thermal stress in TSV structures caused by crystallinity of electroplated copper interconnections

Twice-etched silicon approach for via-last through-silicon-via with a Parylene-HT liner

Air-gap/SiO2 liner TSVs with improved electrical performance

An ultra-fast temporary bonding and release process based on thin photolysis polymer in 3D integration

Copper micro and nano particles mixture for 3D interconnections application

A holistic view of chip-level thermal architecture from heterogeneous stacked dice to system level in telecoms applications

Thermal simulation of heterogeneous GaN/ InP/silicon 3DIC stacks

Temperature-aware online testing of power-delivery TSVs

Graphite-based heat spreaders for hotspot mitigation in 3D ICs

Active Si interposer for 3D IC integrations

Processing active devices on Si interposer and impact on cost

Silicon interposer platform with low-loss through-silicon vias using air

Stress management strategy to limit die curvature during silicon interposer integration

2014 International 3D Systems Integration Conference (3DIC)

2013 IEEE International 3D Systems Integration Conference (3DIC)

2011 IEEE International 3D Systems Integration Conference (3DIC), 2011 IEEE International

2010 IEEE International 3D Systems Integration Conference (3DIC)

2009 IEEE International Conference on 3D System Integration

Computing in 3D

Content Provider	IEEE Xplore Digital Library
Author	Franzon, P.D. Rotenberg, E. Davis, W.R. Tuck, J. Huiyang Zhou Schabel, J. Zhenquian Zhang Dwiel, J.B. Forbes, E. Huh, J. Tshibangu, M. Lipa, S.
Copyright Year	2015
Description	Author affiliation: Dept. of Electr. & Comput. Eng., North Carolina State Univ., Raleigh, NC, USA (Franzon, P.D.; Rotenberg, E.; Davis, W.R.; Tuck, J.; Huiyang Zhou; Schabel, J.; Zhenquian Zhang; Dwiel, J.B.; Forbes, E.; Huh, J.; Tshibangu, M.; Lipa, S.)
Abstract	3DIC technology refers to stacking and interconnecting chips and substrates (“interposers”) with Through Silicon Vias (TSVs). Industry is gearing up for widespread introduction of this technology with the 22 nm node. We have been pursuing a range of approaches to enable low power computing. As well as 3DIC these include heterogeneous computing, powered optimized SIMD units, optimized memory hierarchies, and MPI with post-silicon customized interconnect. Heterogeneous computing refers to the concept of building a mix of CPUs and memories that in turn enable in-situ tuning of the compute load to the compute resources. We introduce the concept of Fast Thread Migration using 3DIC technologies. We present the design of a power optimized SIMD unit in which over half of the power is employed in the FP units. A parallel computer is built using an MPI paradigm. Codes are analyzed so that the MPI interconnect can be power optimized post-silicon. Emerging 3D memories have potential to be employed as Level 2 and Level 3 caches, and this is explored using the Tezzaron 3D memory. As scaling and power optimization occurs, the main memory increasingly dominates the power consumption. Possible extensions to Cortical Processing are discussed.
File Size	948365
File Format	PDF
e-ISBN	9781467393850
DOI	10.1109/3DIC.2015.7334571
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2015-08-31
Publisher Place	Japan
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Computers Three-dimensional displays Low-power computing 3DIC Conferences Integrated circuit interconnections Random access memory TSV Switches Fabrics
Content Type	Text
Resource Type	Article

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