NDLI: A new FIFO design enabling fully-synchronous on-chip data communication network

Content Provider	IEEE Xplore Digital Library
Author	Elrabaa, M.E.S.
Copyright Year	2011
Description	Author affiliation: Computer Engineering Department, King Fahd University for Petroleum and Minerals, Dhahran, Saudi Arabia (Elrabaa, M.E.S.)
Abstract	A new FIFO design that enables fully synchronous circuits with unrelated clocks to communicate synchronously is proposed. Not only would every circuit be running on its own clock, but the interconnection network is fully synchronous and runs at an unrelated clock of its own. With relatively low gate count, the proposed FIFO allows communicating circuits to put/get data at their respective frequencies (1 datum/clock cycle) till it gets filled then the rates converge to the lower frequency. The maximum initial latency is 3 cycles of the consumer's clock. Several manifestations of the proposed FIFO have been developed for different design cases including data width mismatch between producer and consumer. The operation of different FIFOs has been verified using gate-level simulations for several ratios of clock frequencies. An 8-cell FIFO has been designed at the transistor-level and Spice simulations using a 0.13 μm, 1.2V technology has been carried out. It shows proper operation at producer and consumer clock frequencies of 2GHz and 3.125GHz, respectively, with a data transfer rate of more than 2Giga datum/second and an average power of 721 μW.
Starting Page	1
Ending Page	6
File Size	123077
Page Count	6
File Format	PDF
ISBN	9781457700682
e-ISBN	9781457700699
e-ISBN	9781457700675
DOI	10.1109/SIECPC.2011.5877006
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2011-04-24
Publisher Place	Saudi Arabia
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	GALS Data Synchronization Pipelines System-on-Chip Network-on-Chip Logic gates System-on-a-chip Synchronization Clocks Diffusion tensor imaging Pipeline processing
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Mr. Siddhartha Mukherjee siddhartha@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	ndl-support@iitkgp.ac.in
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