NDLI: Phase-locked loop simulations using the latency insertion method

Content Provider	IEEE Xplore Digital Library
Author	Schutt-Aine, J.E. Goh, P.K.
Copyright Year	2013
Description	Author affiliation: Dept. of Electr. & Comput. Eng., Univ. of Illinois at Urbana-Champaign, Urbana, IL, USA (Schutt-Aine, J.E.; Goh, P.K.)
Abstract	In this paper we present a novel and simple behavioral model based simulation method for PLLs. We also demonstrate the use of LIM for simulating PLLs. The methods exploit the latency in the PLL formulation and utilize a leapfrog time-stepping discretization scheme to solve for the transient response of the PLL. Various PLL dynamic responses such as lock-in, pull-in and pull-out conditions are simulated and comparisons with analytical solutions are depicted when available. Due to the formulation in the voltage-phase domain, the method does not suffer from the dual time scale problem which is a main issue in full transistor level simulations of PLLs.
Sponsorship	IEEE Peru Sect.
Starting Page	1
Ending Page	4
File Size	374953
Page Count	4
File Format	PDF
ISBN	9781467348973
e-ISBN	9781467349000
DOI	10.1109/LASCAS.2013.6519090
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2013-02-27
Publisher Place	Peru
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Computational modeling Voltage-controlled oscillators Simulation Detectors Mathematical model Voltage controlled oscillators Phase locked loops Integrated circuit modeling Phase-locked loop (PLL) Tuning
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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