NDLI: Recent Developments on Mapping Reversible Circuits to Quantum Gate Libraries

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2014 Fifth International Symposium on Electronic System Design

2013 International Symposium on Electronic System Design

2012 International Symposium on Electronic System Design (ISED)

Table of contents

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[Invited Talks - 2 abstracts]

Synthesis of Reversible Circuits Using Decision Diagrams

Cleaning Up: Garbage-Free Reversible Circuits by Design Languages

Synthesis of Toffoli Networks: Status and Challenges

Recent Developments on Mapping Reversible Circuits to Quantum Gate Libraries

A Design of 6-bit 125-MS/s SAR ADC in 0.13-µm MM/RF CMOS Process

A 4-bit Asynchronous Binary Search ADC for Low Power, High Speed Applications

0.5 V, Low Power, 1 MHz Low Pass Filter in 0.18 µm CMOS Process

Design Space Exploration and Synthesis of CMOS Low Noise Amplifiers

FPGA Based Efficient Fast FIR Algorithm for Higher Order Digital FIR Filter

Effect of Finite Gain and Bandwidth of Feed-Forward Compensated OTA on Active-RC Integrators: A Case Study

Systolic Variable Length Architecture for Discrete Fourier Transform in Long Term Evolution

SoC Time to Market Improvement through Device Driver Reuse: An Industrial Experience

Confidence Based Power Aware Testing

A Value Propagation Based Equivalence Checking Method for Verification of Code Motion Techniques

High Speed Generic Network Interface for Network on Chip Using Ping Pong Buffers

Analysis and Operation of FPGA-based Hybrid Active Power Filter for Harmonic Elimination in a Distribution System

FPGA Implementation of Particle Filter Based Object Tracking in Video

Post Silicon Validation of Digital Radio Interfaces

Design of a Self-Reconfigurable Adder for Fault-Tolerant VLSI Architecture

A New Assist Technique to Enhance the Read and Write Margins of Low Voltage SRAM Cell

A Modified Twin Precision Multiplier with 2D Bypassing Technique

Improved Design of High-Radix Signed-Digit Adders

Systolic FIR Filter Design with Various Parallel Prefix Adders in FPGA: Performance Analysis

Comparison of FFT/IFFT Designs Utilizing Different Low Power Techniques

Dynamic Sharing of On-Chip Scratchpad Memory on Embedded Platforms

GPU-based Parallel Implementation of SAR Imaging

Design and Analysis of a Robust, High Speed, Energy Efficient 18 Transistor 1-bit Full Adder Cell, Modified with the Concept of MVT Scheme

CSP-Filling: A New X-Filling Technique to Reduce Capture and Shift Power in Test Applications

Improvements for High Performance Elliptic Curve Cryptosystem Processor over GF(2^163)

High Speed Hardware for March C¯

Bridging Validation and Automatic Test Equipment (ATE) Environment

A Process Variation Tolerant Low Contention Keeper Design for Wide Fan-In Dynamic OR Gate

Design of Hardware for Deterministic Nagel-Schreckenberg Traffic Model

Design, Development and Testing of a DSP Based Dynamic Voltage Restorer

Identifying Faulty TSVs in 3D Stacked IC during Pre-bond Testing

Finding Critical Components in Embedded Control Systems Sensitive to Quality-Faults

Application Mapping Onto Mesh-of-Tree Based Network-on-Chip Using Discrete Particle Swarm Optimization

e-SURAKSHAK: A Cyber-Physical Healthcare System with Service Oriented Architecture

From Requirements and Scenarios to ESL Design in SystemC

Multiple Dilution Sample Preparation Using Digital Microfluidic Biochips

Design of a Static Current Simulator Using Device Matrix Approach

Analysis of Contact Resistance Effect on Performance of Organic Thin Film Transistors

Low-Cost Dilution Engine for Sample Preparation in Digital Microfluidic Biochips

Design of 4-Bit Array Multiplier Using Multi-wall Carbon Nanotube Interconnects

The Impact of Process-Induced Mechanical Stress in Narrow Width Devices and Circuit Design Issues

A Test Design for Quick Determination of Incoherency in Chip Multiprocessors' Cache Realizing MOESI Protocol

SD2D: A Novel Routing Architecture for Network-on-Chip

Particle Swarm Optimization Based Circuit Synthesis of Reversible Logic

Fractional Interpretation of Anomalous Diffusion and Semiconductor Equations

Efficient and Compact Electrical Modeling of Multi Walled Carbon Nanotube Interconnects

Design of Fault Tolerant Reversible Arithmetic Logic Unit in QCA

Reversible Logic Circuit Synthesis Using Genetic Algorithm and Particle Swarm Optimization

Electrooculogram Based Online Control Signal Generation for Wheelchair

System on Biochips: A New Design for Integration of Multiple DMFBs

Analysis of Top and Bottom Contact Organic Transistor Performance for Different Technology Nodes

Improvement in Target Detectability Using Spread Spectrum Radar in Dispersive Channel Condition

Multi-objective Low-Power CDFG Scheduling Using Fine-Grained DVS Architecture in Distributed Framework

Signal Stepping Based Multimode Multi-threshold CMOS Technique for Ground Bounce Noise Reduction in Static CMOS Adders

An Improved Soft Switching DC-DC Converter for Low Power PV Applications

Modeling, Analysis and Design of Synchronous Buck Converter Using State Space Averaging Technique for PV Energy System

Enhancement of Medical Ultrasound Images Using Multiscale Discrete Shearlet Transform Based Thresholding

Performance Analysis of Offloading IPsec Processing to Hardware Based Accelerators

A Closed-Loop Control Strategy for Glucose Control in Artificial Pancreas Systems

A Delaunay Triangulation Preprocessing Based Fuzzy-Encroachment Graph Clustering for Large Scale GIS Data

Fractal Image Compression Using Fast Context Independent HV Partitioning Scheme

Energy Aware Spectrum Decision Framework for Cognitive Radio Networks

Policy Based ACL Configuration Synthesis in Enterprise Networks: A Formal Approach

2011 International Symposium on Electronic System Design

2010 International Symposium on Electronic System Design

Recent Developments on Mapping Reversible Circuits to Quantum Gate Libraries

Content Provider	IEEE Xplore Digital Library
Author	Miller, D.M. Sasanian, Z.
Copyright Year	2012
Description	Author affiliation: Dept. of Comput. Sci., Univ. of Victoria, Victoria, BC, Canada (Miller, D.M.; Sasanian, Z.)
Abstract	This paper reviews recent developments on mapping reversible circuits to libraries of elementary quantum gates. The emphasis is on optimization of both the initial reversible circuit and the resulting quantum circuit. At the quantum level, improved realizations of single mixed-polarity multiple-control Toffoli gates are presented as well as techniques for performing quantum gate optimizations across Toffoli gate boundaries. Experimental results show the effectiveness of the methods presented using circuits from the REVLIB benchmark suite.
Sponsorship	IEEE Circuits Syst. Soc.
Starting Page	17
Ending Page	22
File Size	354828
Page Count	6
File Format	PDF
ISBN	9781467347044
DOI	10.1109/ISED.2012.81
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2012-12-19
Publisher Place	India
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Reversible circuits; quantum gates; optimization
Content Type	Text
Resource Type	Article

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