NDLI: FPGA implementation of mono and stereo inverse perspective mapping for obstacle detection

Content Provider	IEEE Xplore Digital Library
Author	Botero, D. Piat, J. Chalimbaud, P. Devy, M. Boizard, J.-L.
Copyright Year	2012
Description	Author affiliation: LAAS / CNRS, University of Toulouse; UPS, INSA, INP, ISAE, 7 avenue du colonel Roche, F-31077 Toulouse Cedex 4, France (Botero, D.; Piat, J.; Chalimbaud, P.; Devy, M.; Boizard, J.-L.)
Abstract	This paper presents the implementation of real time Inverse Perspective Mapping algorithms on a FPGA. The IPM is a spatiotemporal algorithm that allows the detection of obstacles from two images I1 and I2, either acquired by a moving camera, or by a stereoscopic sensor, knowing the relative positions between the two view points. In the case of mono Inverse Perspective Mapping (MIPM), the homography is based on movement information (odometry) while in the case of stereo-inverse perspective mapping (SIPM), the homography depends on the inter-ocular distance. For MIPM, a co-design approach is proposed to compute the homography matrix using a soft-processor. For SIPM, a pre-computed table that encodes simultaneously the homography transformation and the lens distortion correction is used. We present an optimized architecture to implement a real time homographic transformation using a SDRAM memory, which is cheaper than the SRAM. The algorithms are intended to work at least at 30 fps with a VGA image resolution, they are evaluated using two different platforms: a Xilinx Virtex 6 development kit for MIPM, and Altera Cyclone 2 based custom board for SIPM.
Starting Page	1
Ending Page	8
File Size	1815782
Page Count	8
File Format	PDF
ISBN	9781467320894
e-ISBN	9782953998726
e-ISBN	9782953998740
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2012-10-23
Publisher Place	Germany
Access Restriction	Subscribed
Rights Holder	ECSI
Subject Keyword	Cache memory Computer architecture Cameras Mathematical model SDRAM Equations Field programmable gate arrays
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Mr. Siddhartha Mukherjee siddhartha@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	ndl-support@iitkgp.ac.in
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9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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