NDLI: A methodology for the test of embedded compiled cells

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A highly automated design system for rapid development from architecture to ASICs

A hierarchical cell based engineering system for the design of semi-custom analog integrated circuits

Constraint propagation and design interaction in an object orientated IC design environment

Integration of algorithmic VLSI synthesis with testability incorporation

Boolean decomposition of programmable logic arrays

Bridge: a behavioral synthesis system for VLSI

A knowledge-based SPICE environment for improved convergence and user friendliness

ADOPT-a CAD system for analog circuit design

Automatic generation of behavioral simulation models using functional abstraction

Evaluation of macro models for mixed analog/digital circuits

A mixed-mode analog-digital simulation methodology for full custom designs

Wide operating voltage range and low power consumption EPROM structure for consumer oriented ASIC applications

Configurable EEPROMS for ASICS

Transparent-refresh DRAM (TReD) using dual-port DRAM cell

An experimental 2-bit/cell storage DRAM for macro cell or memory-on-logic application

A 185 K*6 field memory for TV/VTR pictures

An 8-bit microcomputer with analog subsystems for implantable biomedical applications

A 4 nsec 4 K*1 bit two-port BiCMOS SRAM

1.7 Gb/s NMOS laser driver

A smart BiCMOS driver for 400 DPI thermal printing heads

High-frequency oscillations n high-pin-count ECL devices

Negative feedback influence on simultaneous switching CMOS outputs

Controlled slew rate output buffer

A fast offset-free sample-and-hold circuit

All MOS on-chip power supply conversion

Finding the steady-state response of analog and microwave circuits

A mixed frequency-time approach for finding the steady-state solution of clocked analog circuits

Mixed-mode simulation tools for custom VLSI designs

Simulation of mixed analog/digital circuits in time-domain by PWL macromodel approach

Parallel electronic circuit simulation on the iPSC system

ADMIT-ADVICE modeling interface tool

RC trees revisited

Floorplanning of hierarchical layout in ASIC environment

Comparison of floorplanning algorithms for full custom ICs

Symbolic design methodology for high-density macro-cell

RISCE-a reduced instruction set circuit extractor for hierarchical VLSI layout verification based on interaction rules

SALIM: a layout generation tool for analog ICs

ILAC: an automated layout tool for analog CMOS circuits

A VLSI implementation of a cellular rotator array

A video rate 16*16 discrete cosine transform IC

A 50 MIPS multiprocessor chip for image processing

Design and implementation of a two-dimensional fast Fourier transform chip

The architectures and design of a 20-MHz real-time DSP

Bit map control processor (BMCP) design

A custom DSP chip to implement a robot motion controller

A reconfigurable 64-tap transversal filter

1 GHz GaAs ADC building blocks

A CMOS 10 bit accuracy and 5 mu S speed AD converter

Multichannel data acquisition system with on-chip digital signal processing

A programmable medical data acquisition system chip

Jitter attenuation phase locked loop using switched capacitor controlled crystal oscillator

A 350 MHz bipolar monolithic PLL

A PLL based clock and data recovery circuit with high input jitter tolerance

Electronic implementation of neuromorphic systems

A programmable analog neural network chip

A self-organizing neural net chip

A digital implementation of a best match classifier

A dynamic programming processor for speech recognition

Speech recognition processors using fuzzy pattern matching

A new multi-algorithm multichannel cascadable digital filter processor

Dense, performance directed, auto place and route

Building block routing-a symbolic approach

An efficient method for custom integrated circuit global routing

A heuristic global router for polycell layout

A two-layer channel routing algorithm for mixed analog and digital signal nets

A power bus channel router

Noise, crosstalk and distortion in mixed analog/digital integrated circuits

Design techniques for fully differential amplifiers

A 10.7-MHz switched-capacitor bandpass filter

A novel parasitic insensitive switched-capacitor technique for realizing very large time constants

Variable scale edge detection of images

A set of 4 IC's in CMOS technology for a programmable hearing aid

BI-CMOS tracking servo LSI for 8 mm VCR

Accurate analog modeling of short channel FETs based o table lookup

An accurate two-dimensional intrinsic capacitance model of short channel MOSFETs

A simple GaAs MESFET model for circuit simulation reflecting the dependence on device geometry and process

Response surface methodology-a modeling tool for integrated circuit designers

Statistical process simulation for CAD/CAM

Modeling modern bipolar technologies to insure design for manufacturability

The effect of contact placement on drive currents in 1.25 mu m gate arrays: measured and simulated

Module generators for both sea of gates and full custom IC's

Measurements of switched capacitor filters generated with a silicon compiler

Physical assembly for analog compilation of high voltage ICs

SPAID: an architectural synthesis tool for DSP custom applications

Efficient controller architectures for DSP compilers

SPEED-a highly flexible slice structure and datapath generator

Automatic synthesis of signal processing benchmark using the CATHEDRAL silicon compilers

A 20 NS CMOS programmable logic device for asynchronous applications

A 2500 gate programmable logic device with subdivisable macrocells

A 9000-gate user-programmable gate array

An architecture for electrically configurable gate arrays

Bus I/O register intensive user-configurable microprocessor peripheral

The EBS-2-an EPROM-based sequencer ASIC

Gate array design productivity: an empirical investigation

BIST using pseudorandom test vectors and signature analysis

Integrated pin electronics for VLSI functional testers

A test system for high speed VLSI array qualification

The loophole in logic test: mixed signal ASIC

Design for testability for mixed analog/digital ASICs

Bottom-up testing methodology for VLSI

A methodology for the test of embedded compiled cells

GaAs low-power shift register and arithmetic logic unit for a high-speed digital signal processor

Design and test of a 2Gb/s GaAs 16/8 bit MUX/DEMUX pair

A 200 Mbps, 60*16 CMOS crosspoint switch

A 100 MegaFlop double precision IEEE multiplier block for advanced bipolar VLSI

A high-speed dynamically reconfigurable 32-bit CMOS adder

A 10 MHz (255, 223) Reed-Solomon decoder

A quasi-passive CMOS pipeline D/A converter

A quad 12 bit DAC with readback and software mode control

A 100 MHz pipelined CMOS comparator for flash A/D conversion

A 667 ns, 12-bit two-step flash ADC

A 10-bit 5 Msample/sec CMOS 2-step flash ADC

A 4-bit 1 GHz sub-half micrometer CMOS/SOS flash analog-to-digital converter using focused ion beam implants

A 13000 gate 3 layer metal bipolar gate array

SH 100E 10000 gate ECL/15000 gate CML gate array family with ECL/TTL I/O compatibility

A 72 K CMOS channellers gate array with embedded 1 Mbit dynamic RAM

A sub half-ns 237 K gate CMOS compacted array

A 120 K-gate usable CMOS sea of gates packing 1.3 M transistors

A high density BiCMOS direct drive array

1.5 Gb/sec data rate communications gate array in GaAs

An ultra-high speed gate array based on 0.6 mu m silicon bipolar technology

DLM/TLM compatible 1.0 mu m gate array with over 100 K usable gates

Overview of ISDN user-network interface

A 13-bit, 160 kHz sigma-delta A/D converter for ISDN

A dual-channel Sigma Delta voiceband PCM codec

Echo canceller design for high speed modems

Real-time string search engine LSI for 800-Mbit/sec LANs

A 16-bit 4'th order noise-shaping D/A converter

Bi-CMOS technology for semi-custom integrated circuits

Process HE: a highly advanced trench isolated bipolar technology for analogue and digital applications

70 ps ECL gate Si bipolar technology using Borosenic-poly process with coupling-base implant

A novel base emitter self-alignment process for high speed bipolar LSIs

Laser customization by direct writing of aluminum interconnects

USLI system models

High performance integrated circuit packaging

Trends in semiconductor packaging, a merchant house view

Accurate measurement of high-speed package and interconnect parasitics

Generalized wiring rules for CMOS circuits

Analysis and guidelines for high-speed VLSI system interconnections

Investigation of power distribution strategies for wafer scale integration (WSI)

A CMOS-based mixed analog-logic standard cell product family

1.2 micron, high speed, high density CMOS analog library

Advanced standard cell library provides high performance mixed digital, analog, and EEPROM single chip solutions

A reduced circuit library design system

A high-speed 16-bit cascadable ALU using an ASPECT standard cell approach

A VLSI chip set for a small mainframe processor

A high performance submicron twin tub V technology for custom VLSI applications

A 0.8 mu m CMOS technology for high performance ASIC memory and channelless gate array

An advanced triple level metal CMOS technology for ASIC applications

Challenges of a vintage 1994 CMOS logic chip

An advanced high voltage CMOS process for custom logic circuits with embedded EEPROM

A SiO/sub x/ resistor load SRAM process for ASIC applications

Unified design methodology and device architecture for multi-generation ASIC applications

A low power, high performance, phone headset amplifier in CMOS technology

An analog front end for full-duplex digital transceivers working on twisted pairs

An analog interface circuit (AIC) for high-speed modems

A single-supply CMOS V.22bis modem analog processor

A fully integrated analog front end LSI for 9600/4800 bps modems

ESD protection structure issues and design for custom integrated circuits

Resistorless ESD protection device for high speed CMOS circuits

Thermal and electrical transients during ESD stress

RELY: a reliability simulator for VLSI circuits

Design methodology for defect tolerant integrated circuits

A circuit breaker for redundant IC systems

Marginal test of DRAMs by masked alpha -radiation

RELIANT: a reliability analysis tool for VLSI interconnects

A 13 bit ISDN-band oversampled ADC using two-stage third order noise shaping

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03222 282435
Mail: ndl-support@iitkgp.ac.in

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Mr. Siddhartha Mukherjee siddhartha@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	ndl-support@iitkgp.ac.in
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7	National Digital Libarray of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
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