NDLI: High-frequency characterization and modeling of polysilicon and diffusion lines

Please wait, while we are loading the content...

2015 IEEE Custom Integrated Circuits Conference (CICC)

Proceedings of the IEEE 2014 Custom Integrated Circuits Conference

Proceedings of the IEEE 2013 Custom Integrated Circuits Conference

Proceedings of the IEEE 2012 Custom Integrated Circuits Conference

2011 IEEE Custom Integrated Circuits Conference (CICC)

IEEE Custom Integrated Circuits Conference 2010

2009 IEEE Custom Integrated Circuits Conference

2008 IEEE Custom Integrated Circuits Conference

2007 IEEE Custom Integrated Circuits Conference

IEEE Custom Integrated Circuits Conference 2006

Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005.

Proceedings of the IEEE 2004 Custom Integrated Circuits Conference (IEEE Cat. No.04CH37571)

Proceedings of the IEEE 2003 Custom Integrated Circuits Conference, 2003.

Proceedings of the IEEE 2002 Custom Integrated Circuits Conference (Cat. No.02CH37285)

Proceedings of the IEEE 2001 Custom Integrated Circuits Conference (Cat. No.01CH37169)

Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044)

Proceedings of the IEEE 1999 Custom Integrated Circuits Conference (Cat. No.99CH36327)

Proceedings of the IEEE 1998 Custom Integrated Circuits Conference (Cat. No.98CH36143)

Proceedings of CICC 97 - Custom Integrated Circuits Conference

Proceedings of Custom Integrated Circuits Conference

Proceedings of the IEEE 1995 Custom Integrated Circuits Conference

Proceedings of IEEE Custom Integrated Circuits Conference - CICC '94

Proceedings of IEEE Custom Integrated Circuits Conference - CICC '93

1992 Proceedings of the IEEE Custom Integrated Circuits Conference

Proceedings of the IEEE 1991 Custom Integrated Circuits Conference

Strategies for CMOS/BiCMOS gate usage on sea-of-gates arrays

A silicon bipolar LSI chip set for 2.4 Gb/s fiber optic transmission

A 50-MHz 10-ns submicron BiCMOS 2-way set associative cache tag memory

New state assignment algorithms for finite state machines using look ahead

IC reliability simulation

A rail-to-rail video-band full Nyquist 8-bit A/D converter

Reversible functional simulation for digital system design

A quasi-complementary-logic GaAs gate array employing air-bridge metallization technology

Performance and technology trade-offs of BiCMOS submicron processes for ASIC applications

A pipelined 9-stage video-rate analog-to-digital converter

Pascant: a partial scan and test generation system

A power efficient channel coder/decoder chip for GSM terminals

A procedural datapath compiler for VLSI full custom applications

2-10 MHz programmable continuous-time 0.05 degrees equiripple linear phase filter

A photodetector array for a one terabyte optical tape recorder

A pragmatic approach to integrated process/device/circuit simulation for IC technology development

Static charge decay analysis of MOS circuits

A single-chip mixed analog/digital signal processor for voiceband applications

A single chip sensor and image processor for fingerprint verification

Submicron CBiCMOS technology with new well and buried layer formed by multiple energy ion implantation

A system for electromigration analysis in VLSI metal patterns

A Six Sigma program implementation

A system for synthesis of sequential machines with built-in testability

A SONET STS-3c user network interface IC

Symbolic verification of CMOS synchronous circuits using characteristic functions

A trainable analog neural chip for image compression

Test considerations for BiCMOS logic families

Timing driven routing and resistivity minimization

A transistor-only current-mode Sigma Delta modulator

10 Mb/s twisted pair CMOS transceiver with transmit waveform pre-equalization

Technology- and power-supply-independent cell library

The use of TCAD in semiconductor technology development

A tool towards integration of IC process, device, and circuit simulation

A 12-bit video BiCMOS track-and-hold amplifier using analog calibration

A vector digital signal processor LSI for speaker-independent voice pattern matching

A 50 MHz variable gain amplifier cell in 2 mu m CMOS

VLSI silicon based prosthesis for in vitro measurement of neural activity

A 50 MHz vision processor

A sub-micron CMOS embedded SRAM compiler

SEAS: a simulated evolution approach for analog circuit synthesis

A 7 MHz 24-bit pipelined accumulator in 1.2- mu m CMOS for application as a numerically controlled oscillator

A 60 V-10 A intelligent power switch using standard cells

1.2 Gb/s integrated laser driver with temperature compensation for modulation current

Integrated digital modulator and analog front-end for GSM digital cellular mobile radio system

An integrated design and characterization environment for the development of a standard cell library

Integrated-circuit reliability simulation including dynamic stress effects

Improving DC convergence in a circuit simulator using a homotopy method

An integrated Si bipolar RF transceiver for a zero IF 900 MHz GSM digital mobile radio frontend of a hand portable phone

Improving BDDs manipulation through incremental reduction and enhanced heuristics

A high speed memory system based on 16 Mb ST (stretchable memory matrix) DRAMs

Hierarchical simulation of hot-carrier induced damages in VLSI circuits

A high speed BiCMOS table look-up gate

Hybrid routing on multichip modules

High performance self-checking adder for VLSI processor

A high performance digital processor for implementing large artificial neural networks

HECTOR: a hierarchical topology-construction program for analog circuits based on a declarative approach to circuit modeling

High-frequency characterization and modeling of polysilicon and diffusion lines

A high density GaAs gate array architecture

GANGLION-a fast hardware implementation of a connectionist classifier

A 10 bit 80 MHz glitchless CMOS D/A converter

2.6 Gbyte/sec bandwidth cache/TLB macro for high-performance RISC processor

Fast simulated diffusion: an optimization algorithm for multi-minimum problems and its application to MOSFET model parameter extraction

FPGA performance versus cell granularity

Fast prototyping of semi-custom bipolar analog ASICs

Field-plated high gain lateral bipolar transistor in standard CMOS process for BiNMOS application

Field programmable gate array key to reconfigurable array outperforming supercomputers

Factors in implementing MCM solutions for the high performance systems of the 1990s

A fully integrated high performance FM stereo decoder

A framework for design for testability of mixed analog/digital circuits

Fully-differential CMOS current-mode circuits

An experimental TDMA modulation/demodulation CMOS VLSI chip-set

Exploiting 0.8-micron ASIC libraries from different venders

An efficient eigenvector-node interchange approach for finding netlist partitions

An error-correcting encoder and decoder for a 1 Gbit/s fiber optic link

A 60-MHz 64-tap echo canceller/decision-feedback equalizer in 1.2- mu m CMOS for 2B1Q high bit-rate digital subscriber line transceivers

An experimental approach to analog fault models

A design tool for weakly nonlinear analog integrated circuits with multiple inputs (mixers, multipliers)

Device sizing for silicon compilers using CSL

A direct sequence BPSK spread spectrum transceiver chip set

DYNAMO: a program for the simulation of transient faults in digital circuits

A dual-port SRAM compiler for 0.8- mu m 100 K BiCMOS gate arrays

The design of a monolithic, signal conditioned pressure sensor

Design model for minority-carrier well-type guard-rings in CMOS circuits

Digital logarithmic CMOS multiplier for very-high-speed signal processing

Device-level analysis of a 1 mu m BiCMOS inverter circuit operating at 77 K using a modified PISCES program

A data-flow processor for real-time low-level image processing

A 32 Mb/s disk drive data separator for constant density recording

DAVE: an automatic mixed analog/digital IC layout compiler

Dynamic asynchronous logic for high speed cMOS systems

A CMOS wideband amplifier with 800 MHz gain-bandwidth

Characterizing a VLSI standard cell library

A CMOS 4 ch*1 k time memory LSI with 1 ns resolution

1 GHz CMOS 12:1 time division MUX/DEMUX pair

Calculation of total dynamic current of VLSI using a switch level timing simulator (RSIM-FX)

A customizable timing controller for electronic imaging applications

A complete single-chip implementation of the JPEG image compression standard

Cell-shifting compaction of building-cell methodology for high-speed GaAs standard-cell LSIs

Can CMOS resist the BiCMOS challenge?

A 170 MHz CMOS pixel processor for windowing graphics

A new on-chip ESD protection circuit with dual parasitic SCR structures for CMOS VLSI

A comparison of methods for supply current analysis

Current-mode logic techniques for CMOS mixed-mode ASICs

A 64 bit CMOS mainframe execution unit macrocell with error detecting circuit

A CMOS 9 bit 25 MHz 100 mW ADC for mixed analog/digital LSIs

A 5-V CMOS line controller with 16-bit audio converters

CMOS IC fault models, physical defect coverage, and I/sub DDQ/ testing

Circuit design for built-in current testing

A two-chip CMOS 64 b mainframe processor chipset

A 14 bit CMOS A/D converter based on dynamic current memories

Current bias testing of differential circuits

A CMOS biquad at VHF

Calculation and application of time-domain waveform sensitivities in asymptotic waveform evaluation

A comparison of an ASIC synthesized design to a schematic entry design for a Viterbi decoder

A 0.5 mu m BiCMOS SOG with selectable 5 V/3.3 V operations

A bonded-SOI-wafer CMOS 16-bit 50-ksps delta-sigma ADC

A 3.3 V, 0.5 mu m BiCMOS technology for BiNMOS and ECL gates

A 1.9 ns BiCMOS CAM macro with double match line architecture

A BiCMOS image sensor with a chopper-stabilized edge detector and a correlated-double-sampling readout circuit for neural network VLSI operating at 77 K

A 0.8- mu m BiCMOS sea-of-gates implementation of the tandem banyan fast packet switch

3.3-V BiCMOS circuit techniques for 250-MHz RISC arithmetic modules

A BiCMOS circuit family for a 0.45 mu m CMOS/BiCMOS sea of gates

An accurate MOS transistor model for submicron VLSI circuit-BSIMplus

ASIC technology applied to SONET multiplex, transmission, and cross-connect equipment

Analog statistical simulation

ACAP-a system for the interactive graphical capture of module generators

Accurate modeling and simulation of bridging faults

An analytical-model generator for interconnect capacitances

The architecture of the GenTest sequential test generator

Automated generation of custom pad cells for ASICs

On applying circular self-test path (CSTP) technique to circuits

Automatic custom layout of analog ICs using constraint-based module generation

Application of boundary-scan and full-chip BIST to a 3 ASIC chip set

An adaptive analog continuous-time CMOS biquadratic filter

Implementation of sub-10 ns serial access mode to a standard 64-Mb DRAM

CCD image sensor with differential, pyramidal output for lossless image compression

Can IDDQ test replace conventional stuck-fault test?

A knowledge based project plan generation and control system for ASIC design management

A 288-kbit fully parallel content addressable memory using stacked capacitor cell structure

New bit line architecture for ultra high speed SRAMs-T-shaped bit line and its real application to 256 k BiCMOS TTL SRAM

A large scale FPGA with 10 K core cells with CMOS 0.8 mu m 3-layered metal process

A new large signal model for heterojunction bipolar transistors including temperature effects

Modelling behaviour and tolerances in analogue cells

A 120 MFLOPS CMOS floating-point processor

Metastability of CMOS master/slave flip-flops

Memory chip for 24-port global register file

A modular flash EEPROM technology for 0.8 mu m high speed logic circuits

A 80 MFLOPS 64-bit microprocessor for parallel computer

A modular memory and process verification vehicle for a sub-micron BiCMOS telecom technology

Mixed mode simulation of slow transient effects in AlGaAs/GaAs HEMT inverters

A 1.5 MLIPS 40-bit AI processor

100 Mpixel/sec single-chip integrated graphics controller (IGC)

A multi-speed digital cross-connect switching VLSI using new circuit techniques in dual port RAMs

Memory synthesis for high speed DSP applications

A 10 bit 75 mega-sample per second A/D converter

A novel three dimensional BiCMOS process using epitaxial lateral overgrowth of silicon

Optimization of field-programmable gate array logic block architecture for speed

Optimal synthesis of high performance architectures

A CMOS 20 MHz 8 bit 50 mW ADC for mixed analog/digital ASICs

Proceedings of the IEEE 1991 Custom Integrated Circuits Conference (Cat. No.91CH2994-2)

IEEE Proceedings of the Custom Integrated Circuits Conference

1989 Proceedings of the IEEE Custom Integrated Circuits Conference

Proceedings of the IEEE 1988 Custom Integrated Circuits Conference

High-frequency characterization and modeling of polysilicon and diffusion lines

Content Provider	IEEE Xplore Digital Library
Author	Eisenstadt, W.R. Bell, O.
Copyright Year	1991
Description	Author affiliation: Dept. of Electr. Eng., Florida Univ., Gainesville, FL, USA (Eisenstadt, W.R.; Bell, O.)
Abstract	Polysilicon interconnect high-frequency measurements (45 MHz to 2 GHz) and SPICE-based transmission-line modeling have been performed on CMOS IC test structures. The methodology consists of the following steps: (1) customized transmission-line layout for microwave coplanar probe-based test; (2) calibration of probe reference plane using the ISS (impedance-standard substrate) standard and the LRM (line-reflect-match) calibration technique; (3) calibration of silicon substrate pad-parasitics; (4) S-parameter measurement of transmission lines and subtraction of system and substrate parasitics; and (5) SPICE circuit model extraction and parameter optimization. Results from ongoing measurements of diffusion lines are also reported.<>
File Size	306394
File Format	PDF
ISBN	0780300157
DOI	10.1109/CICC.1991.164042
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1991-05-12
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Calibration Semiconductor device modeling Transmission lines Integrated circuit modeling Circuit testing Transmission line measurements Integrated circuit interconnections Performance evaluation CMOS integrated circuits Integrated circuit testing
Content Type	Text
Resource Type	Article

Central Library (ISO-9001:2015 Certified)
Indian Institute of Technology Kharagpur
Kharagpur, West Bengal, India | PIN - 721302

See location in the Map
03222 282435
Mail: ndl-support@iitkgp.ac.in

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Mr. Siddhartha Mukherjee siddhartha@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	ndl-support@iitkgp.ac.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Libarray of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in