NDLI: A 24GHz, +14.5dBm fully-integrated power amplifier in 0.18 /spl mu/m CMOS

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2015 IEEE Custom Integrated Circuits Conference (CICC)

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Proceedings of the IEEE 2004 Custom Integrated Circuits Conference (IEEE Cat. No.04CH37571)

Proceedings of the IEEE 2004 Custom Integrated Circuits Conference (IEEE Cat. No.04CH37571)

Proceedings of the IEEE 2004 Custom Integrated Circuits Conference

Welcome to CICC 2004

Steering Committee

Technical Program Committee

Conference overview

Advanced data converter design techniques

Table of contents

Session quick index

Keynote presentation - Session 1

Advanced MOSFET modeling - Session 2

A robust large signal non-quasi-static MOSFET model for circuit simulation

RF distortion analysis with compact MOSFET models

The next generation BSIM for sub-100nm mixed-signal circuit simulation

Estimation of delay variations due to random-dopant fluctuations in nano-scaled CMOS circuits

High-speed serical links - Session 3

A 1.5V 20/30 Gb/s CMOS backplane driver with digital pre-emphasis

10+ Gb/s 90nm CMOS serial link demo in CBGA package

A 4.8-6.4 Gbps serial link for back-plane applications using decision feedback equalization

A low power capacitive coupled bus interface based on pulsed signaling

A 10Gb/s data-dependent jitter equalizer

Analog filters - Session 4

A 0.8V accurately-tuned continuous-time filter

A CMOS gyrator low-IF filter for a dual-mode Bluetooth/ZigBee transceiver [mobile phone applications]

A 1.8V triode-type transconductor and its application to a 10MHz 3/sup rd/-order Chebyshev low pass filter

A 500 MHz OTA-C 4/sup th/ order lowpass filter with class AB CMFB in 0.35 /spl mu/m CMOS technology

Challenges and trade-offs of SOC vs SIP - Session 5

Cellular handset integration -- SIP vs. SOC

MRAM and microprocessor system-in-package: technology stepping stone to advanced embedded devices

23mm/sup 2/ single-chip 0.18/spl mu/m CMOS GPS receiver with 28mW-4.1 mm/sup 2/ radio and CPU/DSP/RAM/ROM

Specialized custom circuits - Session 6

Observation of one-fifth-of-a-clock wake-up time of power-gated circuit

Frequency-hopping vernier clock generators for multiple clock domain SoCs

Device sizing for minimum energy operation in subthreshold circuits

Cross talk countermeasures in inductive inter-chip wireless superconnect

A breakdown voltage doubler for high voltage swing drivers

Simulation and modeling for RF and mixed signal designs - Session 7

An overview of automated macromodelling techniques for mixed-signal systems

Automated extraction of broadly applicable nonlinear analog macromodels from SPICE-level descriptions

Fast, accurate prediction of PLL jitter induced by power grid noise

A modified-Volterra-series technique for improving the accuracy of quasi-static harmonic balance analysis in coupled device and circuit simulation

An efficient algorithm for simulating error vector magnitude in nonlinear OFDM amplifiers

Analysis of envelope signal injection for improvement of RF amplifier intermodulation distortion

High-performance clocking and digital synthesis - Session 8

A 250MHz-2GHz wide range delay-locked loop

A 2.5-3.125 Gb/s quad transceiver with second order analog DLL based CDRs

Notice of Violation of IEEE Publication Principles
A 2-5GHz low jitter 0.13 μm CMOS PLL using a dynamic current matching charge-pump and a noise attenuating loop-filter [frequency synthesizer application]

An improved CMOS ring oscillator PLL with less than 4ps RMS accumulated jitter

A 625 MHz to 10 GHz clock multiplier for re-transmitting 10 Gb/s serial data

A 1.5V direct digital synthesizer with tunable delta sigma modulator in 0.13 /spl mu/m CMOS

High-speed direct digital frequency synthesizers in 0.25-/spl mu/m CMOS

Precision level output devices - Session 9

A 250 mW class D design with direct battery hookup in a 90 nm process [audio band switching amplifier]

A class-D amplifier using a spectrum shaping technique [audio power amplifier]

A delta-sigma modulator for 1-bit digital switching amplifier [audio power amplifier]

Design of high-performance asynchronous sigma delta modulators with a binary quantizer with hysteresis

A study of error sources in current steering digital-to-analog converters

GSM DAC with new segmented mismatch shaping technique

Desien for testability - Session 10

Design considerations and DFT to enable testing of digital interfaces

A digital DFT technique for verifying the static performance of A/D converters

Design-for-digital-testability 30 MHz second-order /spl Sigma/-/spl Delta/ modulator

CMOS scaling and alternatives - Session 11

RFCMOS technology from 0.25/spl mu/m to 65nm: the state of the art

Low power logic circuit and SRAM cell applications with silicon on depletion layer CMOS (SODEL CMOS) technology

Opportunities and challenges in asymmetric device implementation [CMOS device scaling]

MOSFET scaling trends and challenges through the end of the roadmap

ESD protection - Session 12

A 3D mixed-mode ESD protection circuit simulation-design methodology

Power network analysis for ESD robustness in a 90nm ASIC design system

Active-source-pump (ASP) technique for ESD design window expansion and ultra-thin gate oxide protection in sub-90nm technologies

Integrated oscillators and tuning elements - Session 13

Vibrating RF MEMS for next generation wireless applications

A CMOS VCO with 48% tuning range for modern broadband systems

5-GHz in-phase coupled oscillators with 39% tuning range

A temperature-compensated CMOS LC-VCO enabling the direct modulation architecture in 2.4GHz GFSK transmitter

On the selection of on-chip inductors for the optimal VCO design

Custom circuits for interfaces and imaging - Session 14

A 0.13um CMOS ultra-compact DVD SoC employing a full digital equalizing PRML read channel

An improved architecture of the mixed mode clock/data recovery for DVD read channel

A 2W, 92% efficiency and 0.01% THD+N class-D audio power amplifier for mobile applications, based on the novel SCOM architecture

A word-parallel digital associative engine with wide search range based on Manhattan distance

Multiple integration method for high signal-to-noise ratio readout integrated circuit [IR focal plane array applications]

A 256-element CMOS imaging receiver for free-space optical communication

SoC solutions for nanometer desian - Session 15

Proactive design for manufacturing (DFM) for nanometer SoC designs

Design and development of 130-nanometer ICs for a multi-Gigabit switching network system

An electrically robust method for placing power gating switches in voltage islands

Differential transmission line interconnect for high speed and low power global wiring

A soft-error hardened latch scheme for SoC in a 90 nm technology and beyond

Analog IP migration using design knowledge extraction

Advanced memory issues - Session 16

Reviews and future prospects of low-voltage embedded RAMs

BIST controlled variable sense amp timing for 90nm embedded SRAM

Design and implementation of an embedded 512KB level 2 cache subsystem

Process variation in nano-scale memories: failure analysis and process tolerant architecture

Analysis of SRAM neutron-induced errors based on the consideration of both charge-collection and parasitic-bipolar failure modes

RF noise modeling and analysis - Session 17

Analysis and measurements of EM and substrate coupling effects in common RF integrated circuits

Digital noise coupling mechanisms in a 2.4 GHz LNA for heavily and lightly doped CMOS substrates

Crosstalk coupling effects of CMOS co-planar spiral inductors

Noise in passive FET mixers: a simple physical model

Analytical modeling of MOSFET noise parameters for analog and RF applications

Enhanced analytic noise model for RF CMOS design

Measurement and modeling of noise parameters for desensitized low noise amplifiers

Single chip radio solutions for wireless communication - Session 18

Design techniques for a 1-V operation Bluetooth RF transceiver

An ultra-low power 900 MHz RF transceiver for wireless sensor networks

A cost-efficient 0.18 /spl mu/m CMOS RF transceiver using a fractional-N synthesizer for 802.11b/g wireless LAN applications

A CMOS direct-conversion transceiver for IEEE 802.11a/b/g WLANs

A dual channel IF-digitizing IC with 117dB dynamic range at 300Mhz IF for EDGE/GSM base-stations [receiver]

Prop-rammable architectures - Session 19

Platform IC with embedded via programmable logic for fast customization

Designing a via-configurable regular fabric

Hybrid approach to structured ASICs for minimizing the impact of reticle costs and interconnect delay

A 90 nm FPGA I/O buffer design with 1.6 Gbps data rate for source-synchronous system and 300 MHz clock rate for external memory interface

Sequential synthesizable embedded programmable logic cores for system-on-chip

A high performance CMOS programmable logic core

MAX II: A low-cost, high-performance LUT-based CPLD

Memory trends - Session 20

Trends and challenges of large scale embedded memories

SESO memory: A 3T gain cell solution using ultra thin silicon film for dense and low power embedded memories

Advanced ternary CAM circuits on 0.13 /spl mu/m logic process technology

Pure CMOS one-time programmable memory using gate-ox anti-fuse

Evenina panel discussion - Session 21

Evening panel discussion - Session 22

Evening panel discussion - Session 23

Interconnect and noise modeling - Session 24

Relative inductance extraction method

Efficient capacitance extraction method for interconnects with dummy fills

Performance limitation of on-chip global interconnects for high-speed signaling

EPEEC: a compact reluctance based interconnect model considering lossy substrate eddy currents

A surface potential model for predicting substrate noise coupling in integrated circuits

Impact of technology scaling on substrate noise generation mechanisms [mixed signal ICs]

Analysis of coupling noise and it's scalability in dynamic circuits [dynamic logic CMOS ICs]

Full-chip vectorless dynamic power integrity analysis and verification against 100uV/100ps-resolution measurement

Oversampled analog-to-digital converters - Session 25

A 1.2-V 15-bit 2.5-MS/s oversampling ADC with reduced integrator swings

A low-voltage low-power sigma-delta modulator with improved performance in overload condition

Experimental verification of a correlation-based correction algorithm for multi-bit delta-sigma ADCs

Linearity enhancement techniques in low OSR, high clock rate multi-bit continuous-time sigma-delta modulators

Efficient sampling of reference noise in a switched capacitor /spl Sigma//spl Delta/ ADC

A sigma-delta ADC with a built-in anti-aliasing filter for Bluetooth receiver in 130nm digital process

Wireless transmitters - Session 26

Design and manufacturability aspect of SOI CMOS RFICs

An all-digital universal RF transmitter [CMOS RF modulator and PA]

A 5-GHz silicon bipolar transmitter front-end for wireless LAN applications

A CMOS high efficiency +22 dBm linear power amplifier

A 24GHz, +14.5dBm fully-integrated power amplifier in 0.18 /spl mu/m CMOS

A highly integrated quad band low EVM polar modulation transmitter for GSM/EDGE applications

High performance open-loop AM modulator designed for power control of E-GPRS polar modulated power amplifier

Signal and data processors - Session 27

Sandblaster low power DSP [parallel DSP arithmetic microarchitecture]

A 4.75GOPS single-chip programmable processor array consisting of a multithreaded processor and multiple SIMD and IO processors

A baseband processor for pulsed ultra-wideband signals

The performance and experimental results of a multiple bit rate symbol timing recovery circuit for PSK receivers

A XiRisc-based SoC for embedded DSP applications

An image recognition processor using dynamically reconfigurable ALU

Broadband circuits and freguency synthesis - Session 28

A broadband low-noise front-end amplifier for ultra wideband in 0.13 /spl mu/m CMOS

A DC-10GHz linear-in-dB attenuator in 0.13 /spl mu/m CMOS technology

A Ku-band monolithic tuner-LNB for satellite applications [low noise block down-converter]

A 21-27GHz self-shielded 4-way power-combining PA balun

Improved method for measuring frequency ratios in GSM mobile phones

8 GHz, 20mW, fast locking, fractional-N frequency synthesizer with optimized 3/sup rd/ order, 3/5-bit IIR and 3/sup rd/ order 3-bit-FIR noise shapers in 90nm CMOS

A 3.5GHz integer-N PLL with dual on-chip loop filters and VCO tune ports for fast low-IF/zero-IF LO switching in an 802.11 transceiver

Analoa technigues - Session 29

Design considerations of recent advanced low-voltage low-temperature-coefficient CMOS bandgap voltage reference

Optimum area allocation for minimum mismatch [IC device area optimization]

A programmable floating-gate voltage reference in 0.5 /spl mu/m CMOS

A 531 nW/MHz, 128/spl times/32 current-mode programmable analog vector-matrix multiplier with over two decades of linearity

An 8bit 3GHz Si/SiGe HBT sample-and-hold

Variable gain differential current feedback amplifier

Introduction to silicon debug and SoC test - Session 30

The crazy mixed up world of silicon debug [IC validation]

Infrastructure for modular SOC testing

Emerging technigues in SIP and SoC - Session 31

System in package "the rebirth of SIP"

Factors influencing the design of microsystems

Low-noise CMOS integrated sensing electronics for capacitive MEMS strain sensors

10/spl times/ improvement of power transmission over free space using integrated antennas on silicon substrates

A 328 /spl mu/W 5 GHz voltage-controlled oscillator in 90 nm CMOS with high-quality thin-film post-processed inductor

A CMOS 3D camera with millimetric depth resolution

Low power issues for FPGAs - Session 32

Power estimation and thermal budgeting methodology for FPGAs

Low leakage circuit design for FPGAs

A novel low-power FPGA routing switch

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A 24GHz, +14.5dBm fully-integrated power amplifier in 0.18 /spl mu/m CMOS

Content Provider	IEEE Xplore Digital Library
Author	Komijani, A. Hajimiri, A.
Copyright Year	2004
Description	Author affiliation: Dept. of Electr. Eng., California Inst. of Technol., Pasadena, CA, USA (Komijani, A.; Hajimiri, A.)
Abstract	A 24 GHz, +14.5 dBm fully-integrated power amplifier with 50 /spl Omega/ input and output matching is fabricated using 0.18 /spl mu/m CMOS transistors. To enable this, a shielded-substrate coplanar waveguide transmission line structure is used to achieve low loss and small area. The power amplifier achieves a power gain of 7 dB and a maximum single-ended output power of +14.5 dBm with a 3 dB bandwidth of 3.1 GHz, while drawing 100 mA from a 2.8 V supply. The chip area is 1.26 mm/sup 2/.
Sponsorship	IEEE Solid-State Circuits Soc
Starting Page	561
Ending Page	564
File Size	580112
Page Count	4
File Format	PDF
ISBN	0780384954
DOI	10.1109/CICC.2004.1358884
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2004-10-06
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Power amplifiers Coplanar waveguides Impedance Dielectric substrates Conductivity Propagation losses Capacitance Microstrip Differential amplifiers Skin effect
Content Type	Text
Resource Type	Article

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