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2015 IEEE Custom Integrated Circuits Conference (CICC)

Proceedings of the IEEE 2014 Custom Integrated Circuits Conference

Proceedings of the IEEE 2013 Custom Integrated Circuits Conference

Proceedings of the IEEE 2012 Custom Integrated Circuits Conference

2011 IEEE Custom Integrated Circuits Conference (CICC)

IEEE Custom Integrated Circuits Conference 2010

2009 IEEE Custom Integrated Circuits Conference

2008 IEEE Custom Integrated Circuits Conference

2007 IEEE Custom Integrated Circuits Conference

IEEE Custom Integrated Circuits Conference 2006

Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005.

Proceedings of the IEEE 2004 Custom Integrated Circuits Conference (IEEE Cat. No.04CH37571)

Proceedings of the IEEE 2003 Custom Integrated Circuits Conference, 2003.

Proceedings of the IEEE 2002 Custom Integrated Circuits Conference (Cat. No.02CH37285)

Proceedings of the IEEE 2001 Custom Integrated Circuits Conference (Cat. No.01CH37169)

Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044)

Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044)

142 dB /spl Delta//spl Sigma/ ADC with a 100 nV LSB in a 3 V CMOS process

A 20 bit 25 kHz delta sigma A/D converter utilizing frequency-shaped chopper stabilization scheme

A 1 V 1 mW digital-audio /spl Delta//spl Sigma/ modulator with 88 dB dynamic range using local switch bootstrapping

An audio ADC delta-sigma modulator with 100 dB SINAD and 102 dB DR using a second-order mismatch-shaping DAC

A 12-bit 12.5 MS/s multi-bit /spl Delta//spl Sigma/ CMOS ADC

A 8.75-MBaud single-chip digital QAM modulator with frequency-agility and beamforming diversity

Direct digital frequency synthesis of low-jitter clocks

A 2-V 3.7-mW delay locked-loop using recycling integrator correlators for a 5-Mcps DS-CDMA demodulator

A K=3, 2 Mbps low power turbo decoder for 3/sup rd/ generation W-CDMA systems

High-performance flexible all-digital quadrature up and down converter chip

CMOS in the new millennium

Ultra low-power CMOS IC using partially-depleted SOI technology

A fabrication method for high performance embedded DRAM of 0.18 /spl mu/m generation and beyond

NV-SRAM: a nonvolatile SRAM with back-up ferroelectric capacitors

A quick and inexpensive method to identify false critical paths using ATPG techniques: an experiment with a PowerPC/sup TM/ microprocessor

Modular test generation and concurrent transparency-based test translation using gate-level ATPG

Diagnosing resistive bridges using adaptive techniques

A stand-alone integrated excitation/extraction system for analog BIST applications

A new design for complete on-chip ESD protection

Cell characterization for noise stability

Quantitative characterization of substrate noise for physical design guides in digital circuits

Improving embedded software design and integration in SOCs

Coral-automating the design of systems-on-chip using cores

Wire planning for performance and yield enhancement

Probabilistic aspects of crosstalk problems in CMOS ICs

Applying placement-based synthesis for on-time system-on-a-chip design

Methodology for I/O cell placement and checking in ASIC designs using area-array power grid

Architecture of cluster-based FPGAs with memory

Cypress Delta39K/sup TM/. A memory-rich, high performance, scalable CPLD architecture

Dynamic clock management for low power applications in FPGAs

A million gate PLD with 622 MHz I/O interface, multiple PLLs and high performance embedded CAM

Parallel and scalable architecture for solving SATisfiability on reconfigurable FPGA

Spatial-temporal mapping of real applications on a Dynamically Reconfigurable Logic Engine (DRLE) LSI

Field configurable system-on-chip device architecture

CMOS RF design-the low power dimension

A low-power CMOS super-regenerative receiver at 1 GHz

A 1 V, 1 mW, 434 MHz FSK receiver fully integrated in a standard digital CMOS process

A dual-band RF front-end for WCDMA and GSM applications

A 1.2 V, 433 MHz, 10 dBm, 38% global efficiency FSK transmitter integrated in a standard digital CMOS process

Frequency-scalable SiGe bipolar RFIC front-end design

MOS transistor modeling for RF integrated circuit design

BSIMPD: a partial-depletion SOI MOSFET model for deep-submicron CMOS designs

New paradigm of predictive MOSFET and interconnect modeling for early circuit simulation

RFCMOS extension model accurate up to 40 GHz with distributed junction diode

Advanced compact model for short-channel MOS transistors

S-TFT: an analytical model of polysilicon thin-film transistors for circuit simulation

A 64 min single-chip voice recorder/player using embedded 4 bit/cell flash memory

A low-power system-on-chip for the documentation of road accidents

Designing high-speed serial ports using standard ASIC library elements, tools and design methodologies

A 9-M tr. access network system-on-a-chip for mega-bit Internet access at home

A 300 K-gate 0.5 /spl mu/m CMOS implementation of an 8-VSB receiver IC [for HDTV]

Secure contactless smartcard ASIC with DPA protection

A broadband 10 GHz track-and-hold in Si/SiGe HBT technology

A 6-bit 1 GHz acquisition speed CMOS flash ADC with digital error correction

A 100-MSPS 8-b CMOS subranging ADC with parametric operation from 3.8 V down to 2.2 V

A 10-bit, 3 V, 100 MS/s pipelined ADC

A highly linear low-power 10 bit DAC for GSM

A 10-bit 1-GSample/s Nyquist current-steering CMOS D/A converter

Design methodology of the embedded DRAM with the virtual socket architecture

Low-power technique for on-chip memory using biased partitioning and access concentration

A 1.8-V embedded 18-Mb DRAM macro with a 9-ns RAS access time and memory cell efficiency of 33%

An ultra-high-density high-speed loadless four-transistor SRAM macro with a dual-layered twisted bit-line and a triple-well shield

SRAM embedded memory with low cost, flash EEPROM-switch-controlled redundancy

Embedded DRAM: an element and circuit evaluation

Design validation of .18 /spl mu/m 1 GHz cache and register arrays

A CMOS ADSL codec for central office applications

A 4 channel analog front end for central office ADSL modems

A single-chip universal burst receiver for cable modem/digital cable-TV applications

A single chip 155 Mbps/140 Mbps SDH/PDH transceiver

A 450 Mbit/s parallel read/write channel with parity check and 16-state time variant Viterbi

A versatile low-power power line FSK transceiver

An analog front-end LSI with on-chip isolator for V.90 56 kbps modems

Silicon radio integration: architectures and technology: from cartesian zero IF receive & transmit to polar zero I and Q, from silicon bipolar to bulk and SOI CMOS

A 900-MHz T/R switch with a 0.8-dB insertion loss implemented in a 0.5-/spl mu/m CMOS process

Stacked inductors and 1-to-2 transformers in CMOS technology

An integrated capacitively coupled transformer and its application for RF IC's

Measuring and modeling the effects of substrate noise on the LNA for a CMOS GPS receiver

Active substrate noise suppression in mixed-signal circuits using on-chip driven guard rings

Impact of technology scaling on CMOS RF devices and circuits

CMOS DLL based 2 V, 3.2 ps jitter, 1 GHz clock synthesizer and temperature compensated tunable oscillator

A 900 MHz, 2.5 mA CMOS frequency synthesizer with an automatic SC tuning loop

A 2.5-Gb/s clock recovery circuit for NRZ data in 0.4-/spl mu/m CMOS technology

A 65 mW, 0.4-2.3 GHz bandpass filter for satellite receivers

A 3 V linear input range tunable CMOS transconductor and its application to a 3.3 V 1.1 MHz Chebyshev low-pass Gm-C filter for ADSL

A CMOS g/sub m/-C IF filter for Bluetooth

A CMOS readout circuit for pico-ampere thin film pyroelectric array detectors

Effect of technology scaling on digital CMOS logic styles

Boosted gate MOS (BGMOS): device/circuit cooperation scheme to achieve leakage-free giga-scale integration

Power minimization by simultaneous dual-V/sub th/ assignment and gate-sizing

5.5 V tolerant I/O in a 2.5 V 0.25 /spl mu/m CMOS technology

Dynamic current mode logic (DyCML), a new low-power high-performance logic family

A noise-tolerant dynamic circuit design technique

Noise in mixers, oscillators, samplers, and logic an introduction to cyclostationary noise

Complete noise analysis for CMOS switching mixers via stochastic differential equations

Analysis of jitter due to power-supply noise in phase-locked loops

Nonlinear behavioral modeling and simulation of phase-locked and delay-locked systems

Automated extraction of nonlinear circuit macromodels

Finite-length signal quantization using discrete optimization

A 4-tap 125-MHz mixed-signal echo canceller for Gigabit Ethernet on copper wire

A low complexity joint equalizer and decoder for 1000Base-T Gigabit Ethernet

A PN-acquisition ASIC for wireless CDMA systems

Media processor core architecture for realtime, bi-directional MPEG4/H.26X codec with 30 fr/s for CIF-video

Efficient and reusable time-sharing architectures for equalizer structures

A locally-clocked dynamic logic serial/parallel multiplier

On-chip inductance modeling and RLC extraction of VLSI interconnects for circuit simulation

Parasitic extraction for multimillion-transistor integrated circuits: methodology and design experience

Multi-aggressor relative window method for timing analysis including crosstalk delay degradation

Multi-dimensional model reduction of VLSI interconnects

A novel high-performance predictable circuit architecture for the deep sub-micron era

Low power bus coding techniques considering inter-wire capacitances

WiCkeD: analog circuit synthesis incorporating mismatch

On intellectual property protection

An analysis of the design processes required for the technology conversion of SoC intellectual property

Firm IP development: methodology and deliverables

A new paradigm for very flexible SONET/SDH IP-modules

Merging hardware and software: intellectual property cores for Internet applications

VLSI implementation of a realtime wavelet video coder

A partitioned wavelet-based approach for image compression using FPGA's

FLOVA: A four-issue VLIW geometry processor with SIMD instructions and lighting acceleration unit

Novel VLIW code compaction method for a 3D geometry processor

Multi-thread VLIW processor architecture for HDTV decoding

A full accuracy MPEG1 audio layer 3 (MP3) decoder with internal data converters

Physical processes of phase noise in differential LC oscillators

A new approach to fully integrated CMOS LC-oscillators with a very large tuning range

A 1 mA, -120.5 dbc/Hz at 600 kHz from 1.9 GHz fully tuneable LC CMOS VCO

A 10 GHz CMOS distributed voltage controlled oscillator

A 1.8 GHz highly-tunable low-phase-noise CMOS VCO

A fully-integrated low phase-noise nested-loop PLL for frequency synthesis

A low power high spectral purity frequency translational loop for wireless applications

Proceedings of the IEEE 1999 Custom Integrated Circuits Conference (Cat. No.99CH36327)

Proceedings of the IEEE 1998 Custom Integrated Circuits Conference (Cat. No.98CH36143)

Proceedings of CICC 97 - Custom Integrated Circuits Conference

Proceedings of Custom Integrated Circuits Conference

Proceedings of the IEEE 1995 Custom Integrated Circuits Conference

Proceedings of IEEE Custom Integrated Circuits Conference - CICC '94

Proceedings of IEEE Custom Integrated Circuits Conference - CICC '93

1992 Proceedings of the IEEE Custom Integrated Circuits Conference

Proceedings of the IEEE 1991 Custom Integrated Circuits Conference

IEEE Proceedings of the Custom Integrated Circuits Conference

1989 Proceedings of the IEEE Custom Integrated Circuits Conference

Proceedings of the IEEE 1988 Custom Integrated Circuits Conference

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3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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