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2015 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)

2014 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)

2013 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)

2012 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)

2011 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)

2010 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)

2009 IEEE/ACM International Conference on Computer-Aided Design - Digest of Technical Papers

2008 IEEE/ACM International Conference on Computer-Aided Design

2007 IEEE/ACM International Conference on Computer-Aided Design

Conference committee

Table of contents

A fast and high-capacity electromagnetic solution for high- speed IC design

Impedance extraction for 3-D structures with multiple dielectrics using preconditioned boundary element method

Statistical analysis of RF circuits using combined circuit simulator-full wave field solver approach

Slot allocation using logical networks for TDM virtual-circuit configuration for network-on-chip

Run-time adaptive on-chip communication scheme

Using functional independence conditions to optimize the performance of latency-insensitive systems

A geometric approach for early power grid verification using current constraints

Stochastic extended Krylov subspace method for variational analysis of on-chip power grid networks

Parallel domain decomposition for simulation of large-scale power grids

Fast exact toffoli network synthesis of reversible logic

A novel synthesis algorithm for reversible circuits

Checking equivalence of quantum circuits and states

A self-adjusting clock tree architecture to cope with temperature variations

Exploiting STI stress for performance

Automating post-silicon debugging and repair

Practical method for obtaining a feasible integer solution in hierarchical layout optimization

Monte-carlo driven stochastic optimization framework for handling fabrication variability

Gate sizing by lagrangian relaxation revisited

An efficient algorithm for statistical circuit optimization using lagrangian relaxation

Unified adaptivity optimization of clock and logic signals

Incremental component implementation selection: enabling ECO in compositional system synthesis

Exploiting hierarchy and structure to efficiently solve graph coloring as SAT

Finding linear building-blocks for RTL synthesis of polynomial datapaths with fixed-size bit-vectors

Enhancing design robustness with reliability-aware resynthesis and logic simulation

Data locality enhancement for CMPs

Mapping model with Inter-array memory sharing for multidimensional signal processing

Increasing data-bandwidth to instruction-set extensions through register clustering

Optimal polynomial-time interprocedural register allocation for high-level synthesis and ASIP design

An efficient algorithm for time separation of events in concurrent systems

Design, synthesis and evaluation of heterogeneous FPGA with mixed LUTs and macro-gates

Device and architecture concurrent optimization for FPGA transient soft error rate

Design methodology to trade off power, output quality and error resiliency: application to color interpolation filtering

Thermal-aware steiner routing for 3D stacked ICs

Extending systems-on-chip to the third dimension: performance, cost and technological tradeoffs

Strategies for improving the parametric yield and profits of 3D ICs

Scalable exploration of functional dependency by interpolation and incremental SAT solving

Incremental learning approach and SAT model for boolean matching with don’t cares

A performance-driven QBF-based iterative logic array representation with applications to verification, debug and test

The coming of age of physical synthesis

An incremental learning framework for estimating signal controllability in unit-level verification

Stimulus generation for constrained random simulation

Probabilistic decision diagrams for exact probabilistic analysis

Computation of minimal counterexamples by using black box techniques and symbolic methods

Approximation algorithm for the temperature-aware scheduling problem

Procrastination determination for periodic real-time tasks in leakage-aware dynamic voltage scaling systems.

The FAST methodology for high-speed SoC/computer simulation

A novel SoC design methodology combining adaptive software and reconfigurable hardware

Can nano-photonic silicon circuits become an INTRA-chip interconnect technology?

Hybrid cegar: combining variable hiding and predicate abstraction

Automated refinement checking of concurrent systems

Inductive equivalence checking under retiming and resynthesis

A frequency-domain technique for statistical timing analysis of clock meshes

Clustering based pruning for statistical criticality computation under process variations

Timing budgeting under arbitrary process variations

Exploiting symmetry in SAT-based boolean matching for heterogeneous FPGA technology mapping

Combinational and sequential mapping with priority cuts

A general model for performance optimization of sequential systems

Timing constraint-driven technology mapping for FPGAs considering false paths and multi-clock domains

Skew aware polarity assignment in clock tree

Efficient multi-layer obstacle-avoiding rectilinear steiner tree construction

A simultaneous bus orientation and bused pin flipping algorithm

Optimal bus sequencing for escape routing in dense PCBs

Untangling twisted nets for bus routing

Low-overhead design technique for calibration of maximum frequency at multiple operating points

Variation-aware performance verification using at-speed structural test and statistical timing

Estimation of delay test quality and its application to test generation

Efficient path delay test generation based on stuck-at test generation using checker circuitry

Timing variation-aware high-level synthesis

Early planning for clock skew scheduling during register binding

Compatibility path based binding algorithm for interconnect reduction in high level synthesis

Operation chaining asynchronous pipelined circuits

Adaptive post-silicon tuning for analog circuits: concept, analysis and optimization

Sensitivity analysis for oscillators

Yield-aware analog integrated circuit optimization using geostatistics motivated performance modeling

Device-circuit co-optimization for mixed-mode circuit design via geometric programming

Modeling, optimization and control of rotary traveling-wave oscillator

A methodology for fast and accurate yield factor estimation during global routing

Archer: a history-driven global routing algorithm

High-performance routing at the nanometer scale

BoxRouter 2.0: architecture and implementation of a hybrid and robust global router

Cachecompress: a novel approach for test data compression with cache for IP embedded cores

A hybrid scheme for compacting test responses with unknown values

A selective pattern-compression scheme for power and test-data reduction

Methodology for low power test pattern generation using activity threshold control logic

ECO timing optimization using spare cells

Timing optimization by restructuring long combinatorial paths

Engineering change using spare cells with constant insertion

Simultaneous input vector selection and dual threshold voltage assignment for static leakage minimization

Equalized interconnects for on-chip networks: modeling and optimization framework

Intsim: a CAD tool for optimization of multilevel interconnect networks

A fast band-matching technique for interconnect inductance modeling

Formal verification at higher levels of abstraction

Analog placement with common centroid constraints

Temperature aware microprocessor floorplanning considering application dependent power load

3D-STAF: scalable temperature and leakage aware floorplanning for three-dimensional integrated circuits

Variation-aware task allocation and scheduling for MPSoC

A design flow dedicated to multi-mode architectures for DSP applications

The design and synthesis of a synchronous and distributed MAC protocol for wireless network-on-chip

Selective shielding: a crosstalk-free bus encoding technique

Sparse and passive reduction of massively coupled large multiport interconnects

Analysis of large clock meshes via Harmonic-weighted model order reduction and port sliding

Principle Hessian Direction based parameter reduction with process variation

MOSFET Modeling for 45nm and Beyond

Voltage island-driven floorplanning

An ILP algorithm for post-floorplanning voltage-island generation considering power-network planning

Module assignment for pin-limited designs under the stacked-Vdd paradigm

Yield-driven near-threshold SRAM design

Soft-edge flip-flops for improved timing yield: design and optimization

Remote activation of ICs for piracy prevention and digital right management

A nonlinear cell macromodel for digital applications

Including inductance in static timing analysis

A robust finite-point based gate model considering process variations

Victim alignment in crosstalk aware timing analysis

Compact modeling of variational waveforms

Multi-layer interconnect performance corners for variation-aware timing analysis

An efficient method for statistical circuit simulation

A methodology for timing model characterization for statistical static timing analysis

Estimation of statistical variation in temporal NBTI degradation and its impact on lifetime circuit performance

An efficient method to identify critical gates under circuit aging

Efficient computation of current flow in signal wires for reliability analysis

The effect of process variation on device temperature in finFET circuits

BioRoute: a network-flow based routing algorithm for digital microfluidic biochips

Performance and power evaluation of a 3D CMOS/nanomaterial reconfigurable architecture

Fault-tolerant multi-level logic decoder for nanoscale crossbar memory arrays

Combining static and dynamic defect-tolerance techniques for nanoscale memory systems

An efficient wake-up schedule during power mode transition considering spurious glitches phenomenon

Analysis and optimization of power-gated ICs with multiple power gating configurations

Sizing and placement of charge recycling transistors in MTCMOS circuits

Minimizing leakage power in sequential circuits by using mixed vt flip-flops

Efficient decoupling capacitance budgeting considering operation and process variations

Efficient placement of distributed on-chip decoupling capacitors in nanoscale ICs

A novel technique for incremental analysis of on-chip power distribution networks

Architectural power models for sram and cam structures based on hybrid analytical/empirical techniques

Novel wire density driven full-chip routing for CMP variation control

Accurate detection for process-hotspots with vias and incomplete specification

TIP-OPC: a new topological invariant paradigm for pixel based optical proximity correction

A novel intensity based optical proximity correction algorithm with speedup in lithography simulation

Stabilizing schemes for piecewise-linear reduced order models via projection and weighting functions

Parameterized model order reduction via a two-directional Arnoldi process

Efficient VCO phase macromodel generation considering statistical parametric variations

Bounding L2 gain system error generated by approximations of the nonlinear vector field

Variable domain transformation for linear PAC analysis of mixed-signal systems

2006 IEEE/ACM International Conference on Computer Aided Design

ICCAD-2005. IEEE/ACM International Conference on Computer-Aided Design, 2005.

IEEE/ACM International Conference on Computer Aided Design, 2004. ICCAD-2004.

ICCAD-2003. International Conference on Computer Aided Design (IEEE Cat. No.03CH37486)

IEEE/ACM International Conference on Computer Aided Design, 2002. ICCAD 2002.

IEEE/ACM International Conference on Computer Aided Design. ICCAD 2001. IEEE/ACM Digest of Technical Papers (Cat. No.01CH37281)

IEEE/ACM International Conference on Computer Aided Design. ICCAD - 2000. IEEE/ACM Digest of Technical Papers (Cat. No.00CH37140)

1999 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (Cat. No.99CH37051)

1998 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (IEEE Cat. No.98CB36287)

1997 Proceedings of IEEE International Conference on Computer Aided Design (ICCAD)

Proceedings of International Conference on Computer Aided Design

Proceedings of IEEE International Conference on Computer Aided Design (ICCAD)

IEEE/ACM International Conference on Computer-Aided Design

Proceedings of 1993 International Conference on Computer Aided Design (ICCAD)

1992 IEEE/ACM International Conference on Computer-Aided Design

1991 IEEE International Conference on Computer-Aided Design Digest of Technical Papers

1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers

1989 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers

[1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers

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