NDLI: A powerful global router: based on Steiner min-max trees

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Fast test generation for sequential circuits

1989 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers (Cat. No.89CH2805-0)

A powerful global router: based on Steiner min-max trees

Constructing the optimal rectilinear Steiner tree derivable from a minimum spanning tree

A minimum separation algorithm for river routing with bounded number of jogs

Module assignment and interconnect sharing in register-transfer synthesis of pipelined data paths

A new integer linear programming formulation for the scheduling problem in data path synthesis

Scheduling and hardware sharing in pipelined data paths

Automating the diagnosis and the rectification of design errors with PRIAM

Accurate logic simulation in the presence of unknowns

Restricted symbolic evaluation is fast and useful

CRACKER: a general area router based on stepwise reshaping

AGAR: a single-layer router for gate array cell generation

A new approach to sea-of-gates global routing

Manual rescheduling and incremental repair of register-level datapaths

A resource sharing and control synthesis method for conditional branches

A logic synthesis system for VHDL design descriptions

A timing model for static CMOS gates

An accurate timing model for fault simulation in MOS circuits

Event-EMU: an event driven timing simulator for MOS VLSI circuits

Automatic mixed-mode timing simulation

Global refinement for building block layout

Timing driven placement

Combining partitioning and global routing in sea-of-cells design

Layout methods for digital optical computing

Definition and assignment of complex data-paths suited for high throughput applications

Tree-height minimization in pipelined architectures

Synthesis of address generators

Timing models in VAL/VHDL

On the computation of the ranges of detected delay fault sizes

A bounded delay race model

Two-dimensional compaction for placement refinement

A custom cell generation system for double-metal CMOS technology

An O(n log n) algorithm for 1-D tile compaction

An efficient algorithm for layout compaction problem with symmetry constraints

Layout-driven test generation

Optimal granularity of test generation in a distributed system

The critical path for multiple faults

High performance test generation for accurate defect models in CMOS gate array technology

Uninterpreted modeling using the VHSIC hardware description language (VHDL)

Mixed-mode simulation of compiled VHDL programs

Switch-level VHDL descriptions

VHDL modeling for analog-digital hardware designs (VHSIS hardware description language)

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A new methodology for the design centering of IC fabrication processes

Statistical bipolar circuit design using MSTAT

Computation of bus current variance for reliability estimation of VLSI circuits

Boolean minimization and algebraic factorization procedures for fully testable sequential machines

State assignment for initializable synthesis (gate level analysis)

Optimum and heuristic algorithms for finite state machine decomposition and partitioning

State assignment for multilevel logic using dynamic literal estimation

An approach for the yield enhancement of programmable gate arrays

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Fault detection and location in reconfigurable VLSI arrays

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Practicality of state-machine verification of speed-independent circuits

Inserting active delay elements to achieve wave pipelining

A data model and architecture for VLSI/CAD databases

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Optimal layout via Boolean satisfiability

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Pin assignment with global routing

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PLA decomposition with generalized decoders

An exact minimizer for Boolean relations

WireLisp: combining graphics and procedures in a circuit specification language

Fast incremental netlist compilation of hierarchical schematics

Structure optimization in logic schematic generation

A new approach to optimal cell synthesis

CLEO: a CMOS layout generator

An optimal transistor-chaining algorithm for CMOS cell layout

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Design of sequential machines for efficient test generation

Test generation for highly sequential circuits

FACT-a testability analysis methodology

Analogue circuit optimization in a graphical environment

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The EVE VLSI information management environment

Interconnection length estimation for optimized standard cell layouts

Early matching of system requirements and package capabilities

A clock distribution scheme for nonsymmetric VLSI circuits

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Waveform relaxation for transient simulation of two-dimensional MOS devices

Synthesis of delay fault testable combinational logic

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Routing using a pyramid data structure

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Functional comparison of logic designs for VLSI circuits

Specification and verification of VLSI systems

Dynamic redundancy identification in automatic test generation

FANHAT: fanout oriented hierarchical automatic test generation system

Exact critical path tracing fault simulation on massively parallel processor AAP2

High-speed compiled-code simulation of transition faults

An algorithm for hierarchical floorplan design

Constrained floorplan design for flexible blocks

Multi-terrain partitioning and floor-planning for data-path chip (microprocessor) layout

Hierarchical compiled event-driven logic simulation

A model for comparing synchronization strategies for parallel logic-level simulation

Portable parallel logic and fault simulation

Modeling the driving-point characteristic of resistive interconnect for accurate delay estimation

Modeling uncertainty in RC timing analysis

Critical path issue in VLSI design

PACE2: an improved parallel VLSI extractor with parameter extraction

C3DSTAR: a 3D wiring capacitance calculator

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New ATPG techniques for logic optimization

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A diagnosis method using pseudo-random vectors without intermediate signatures

[1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers

A powerful global router: based on Steiner min-max trees

Content Provider	IEEE Xplore Digital Library
Author	Chiang, C. Sarrafzadeh, M. Wong, C.K.
Copyright Year	1989
Description	Author affiliation: Dept. of Electr. Eng. & Comput. Sci., Northwestern Univ., Evanston, IL, USA (Chiang, C.; Sarrafzadeh, M.)
Abstract	A study is made of the global routing of multiterminal nets. The authors propose a novel global router. Each step consists of finding a tree, called Steiner min-max tree, that is, a Steiner tree with the maximum-weight edge minimized (real vertices represent channels containing terminals of a net, Steiner vertices represent intermediate channels, and weights correspond to densities). An efficient algorithm is presented for obtaining a Steiner min-max tree, in a weighted graph. Experimental results on difficult examples, randomly generated data, master slice chips, and benchmark examples from the physical design workshop are very promising. (In all cases, previous results have been improved.).<>
Starting Page	2
Ending Page	5
File Size	306996
Page Count	4
File Format	PDF
ISBN	0818619864
DOI	10.1109/ICCAD.1989.76892
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1989-11-05
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Steiner trees Routing Tree graphs Tiles Circuits Joining processes Wiring Simulated annealing Polynomials Power generation
Content Type	Text
Resource Type	Article

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