NDLI: Improving the proportion of at-speed tests in scan BIST

Content Provider	IEEE Xplore Digital Library
Author	Huang, Y. Pomeranz, I. Reddy, S.M. Rajski, J.
Copyright Year	2000
Description	Author affiliation: Dept. of Electr. & Comput. Eng., Iowa Univ., Iowa City, IA, USA (Huang, Y.)
Abstract	A method to select the lengths of functional sequences in a BIST scheme for scan designs is proposed in this paper. A functional sequence is a sequence of primary input vectors applied when the circuit operates as a sequential circuit, without using scan. These sequences can be applied at-speed, i.e., at the normal circuit clock speed. The objectives set for choosing the lengths of the functional sequences are to increase the number of vectors applied at-speed, and to reduce the number of settings of functional sequence lengths, without compromising the fault coverage achieved. The experimental results presented demonstrate that compared to earlier methods, the proposed method achieves the above objectives while also achieving higher fault coverages for most of the benchmark circuits considered.
Starting Page	459
Ending Page	463
File Size	511930
Page Count	5
File Format	PDF
ISBN	0780364457
ISSN	10923152
DOI	10.1109/ICCAD.2000.896514
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2000-11-05
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Built-in self-test Clocks Circuit testing Frequency Circuit faults Sequential circuits Power dissipation Benchmark testing System testing Design optimization
Content Type	Text
Resource Type	Article
Subject	Computer Graphics and Computer-Aided Design Software Computer Science Applications

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