NDLI: A low power 0.13µm ADC for drift chambers

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ICECS 2009 table of contents

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Class-AB output stage design for high-speed three-stage op-amps

Design considerations for fast-settling two-stage Miller-compensated operational amplifiers

Current conveyor based amplifier and adaptive buffer for use in an analog frontend

Low voltage low power techniques in design of zero IF CMOS receivers

A 3.1-10.6 GHz RF CMOS circuits monolithically integrated with dipole antenna

Radio frequency tunable polyphase filter design

Low-power high-linearity 0.13-µm CMOS WCDMA receiver front-end

Low power 3-5GHz RF receiver frontend for IEEE 802.15.4a UWB WPAN in 0.13-µm CMOS

A low-power continuous-time incremental 2nd-order-MASH ΣΔ-modulator for a CMOS imager

Second-order multi-bit ΣΔ ADC using a Pulse-Width Modulated DAC and an integrating quantizer

A double-sampled hybrid CT/DT SMASH ΣΔ modulator for wideband applications

A double-sampling cross noise-coupled split ΣΔ-modulation A/D converter with 80 dB SNR

A multi-bit cascaded sigma-delta modulator with an oversampled single-bit DAC

Delay-based dual-rail pre-charge logic

Analysis of the impact of random process variations in CMOS tapered buffers

Design of a balanced 8-modulus RNS

Novel high speed and ultra low voltage CMOS flip-flop

Asynchronous logic for high variability nano-CMOS

Definition of an innovative filling structure for digital blocks : the DFM filler cell

Custom layout strategy for rectangle-shaped log-depth multiplier reduction tree

An automated design methodology for layout generation targeting power leakage minimization

Leakage Power Analysis attacks: Theoretical analysis and impact of variations

An energy-aware multiplier based on a Configurable-Reuse of points design methodology

A PLL configuration for reducing both incoming and inherent jitters

Efficient cascaded VLSI FFT architecture for OFDM systems

High Throughput architecture for OCTAGON Network on Chip

Power efficient Networks on Chip

High throughput scalable Motion Compensation architecture for H.264/SVC video coding standard

A reverse converter for the new 4-moduli set {2n + 3, 2n + 2, 2n + 1, 2n}

Adaptive multirate signal estimation with lattice orthogonalization

An FFT core for DVB-T2 receivers

A new horizontal and vertical common subexpression elimination method for multiple constant multiplication

An efficient RNM compensation topology with voltage buffer and nulling resistors for large-capacitive-load three-stage OTAs

A high-speed low-power output buffer amplifier for large-size LCD applications

Low-voltage differential amplifier

Offset cancellation with subthreshold-operated feedback circuit for fully differential amplifiers

Ultra low voltage semi-floating-gate transconductance amplifier based on binary inverters

A 0.9-V programmable true piecewise approximation logarithmic amplifier in 0.13µm CMOS technology

A self biased operational amplifier at ultra low power supply voltage

Exploitation of the phasor approach for closed-form solution of the Van der Pol's oscillator and sinusoidal oscillators with high-order nonlinearity

Low-voltage CMOS voltage squarer

A heterogenous approach to symbolic calculations based on structural numbers

A low leakage single supply level shifter design for multi voltage systems

A charge sampling baseband filter using a new high linearity Gm for multimode receiver

A switched-capacitor CMOS voltage reference for ultra low-voltage and ultra low-power operation

Wideband reconfigurable CMOS Gm-C filter For wireless applications

A new low voltage bandgap reference topology

A programmable active-RC complex filter for wireless communications

A $4^{th}$ order CMOS 65nm wideband low power analog filter for wireless receivers

An experimental 0.6-V 57.5-fJ/conversion-step 250-kS/s 8-bit rail-to-rail successive approximation ADC in 0.18µm CMOS

E-Shaped Patch Antenna modeling with MoM and RWG basis functions

A 130nm CMOS tunable digital frequency divider for dual-band microwave radiometer

Error control in circuit transient analysis

An analysis of wireless inductive coupling for High Data Rate biomedical telemetry using a new VHDL n-PSK modulator

Wearable wireless sensor for the gait monitorization of Parkinsonian patients

An all-digital ADC/TDC for sensor interface with TAD architecture in 0.18-µm digital CMOS

Low actuation voltage silicon carbide RF switches for MEMS above IC

A 32 × 32 channels, $3-cm^{2},$ 555-mW chip for X-ray pixel detector read-out

An inverse scattering approach using hybrid PSO-RBF network for microwave imaging purposes

An integrated model of a wireless power transportation for RFID and WSN applications

Shielding structures for millimeter-wave integrated transformers

Radiation pattern analysis of conical horn using wavelet-based moment method

Equivalent circuit model of the TEM cell electric and magnetic field coupling to microstrip lines

Applications of evolutionary computation techniques to analog, mixed-signal and RF circuit design - an overview

Doping profile optimization in semiconductor design

Optimizing current conveyors by evolutionary algorithms including differential evolution

Application of MO-TRIBES to the design of analog electronic circuits

Less expensive and high quality stopping criteria for MC-based analog IC yield optimization

A $0.0027-mm^{2}$ 9.5-bit 50-MS/s all-digital A/D converter TAD in 65-nm digital CMOS

Optimum clock slope for flip-flops within a clock domain: Analysis and a case study

Reducing test power dissipation with novel power gating implementation

The design of multiple-precision floating-point multiplier with SIMD support

Scoring criteria for the selection of capacitors in DC to DC converters design

Efficienct LED driver with an adaptive reference tracking technique

A unified model for filter capacitor constraints in DC to DC switching converters design

Integrated stabilized photovoltaic energy harvester

MAC protocol implementation in RF-MIMO WLAN

Integration of WLAN, UMTS and WiMAX in 4G

Reduction of TCP instability in multi-hop IEEE802.11 ad hoc networks

VLSI implementation of a multi-standard MIMO symbol detector for 3GPP LTE and WiMAX

Methodology of a system level design for a Cognitive Radio receiver “application for IEEE 802.22 Standard”

Programmable Motion Estimation architecture

Discretization methods of fractional parallel PID controllers

Power efficient architecture for motion estimation using the QSDS-DIC algorithm

Robust estimation of LP parameters in white noise with unknown variance

Asynchronous design: A promising paradigm for electronic circuits and systems

The Amulet chips: Architectural development for asynchronous microprocessors

Current trends in high-level synthesis of asynchronous circuits

Updates on the potential of clock-less logics to strengthen cryptographic circuits against side-channel attacks

On the trade-off between resolution time and delay times in bistable circuits

Multi-mode baseband transmit path for EDGE, TD-SCDMA, and WCDMA in 45-nm CMOS

A low-dropout regulator with smooth peak current control (SPCC) topology for over current protection

A 250MHz Gm-C filter using negative current feedback OTAs

A low-voltage low-power comparator With current-controlled dynamically-biased preamplifiers For DCM buck regulators

A 1.21V, 100mA, 0.1µF–10µF output capacitor low drop-out voltage regulator for SoC applications

Comparative study of recent advances in power amplification devices and circuits for wireless communication infrastructure

Performance assessment of RF power amplifier memory polynomial models under different signal statistics

A low-power 0.4-22GHz CMOS cascode distributed amplifier for optical communication systems

Improved inverse class-E matching network for microwave high power amplifiers

A new architecture for low-power high-speed pipelined ADCs using double-sampling and opamp-sharing techniques

Synthesis of complex subband Hybrid Filter Banks A/D converters using adaptive filters

Analysis of the linearity of pipelined ADC due to capacitor non-linearity

A low power 0.13µm ADC for drift chambers

A low-power architecture for integrating analog-to-digital converters

A design methodology for high-performance and low-leakage fixed-point transpose FIR filters

Efficient mapping on FPGA of convolution computation based on combined CSA-CPA accumulator

Exploring performance-power trade-offs for look-up tables in SRAM-based FPGAs

Two level decomposition based matrix multiplication for FPGAs

Unbalanced FIFO sorting for FPGA-based systems

Optical NoC design-parameters exploration and analysis

A multi level functional verification of multistage interconnection network for MPSOC

Sensitivity based parameter reduction for statistical analysis of circuit performance

On the accuracy of Elmore-based Delay Models

Structurally synthesized multiple input BDDs for simulation of digital circuits

General synthesis method for cylindrical antenna arrays for directive and conformal pattern

Steering an adaptive antenna array by LMS algorithm

Multi-User multiple antenna systems in Up-Link OFDM communications

Improvement technique of channel estimation in OFDM-MIMO systems

A novel CMOS all-pass tunable phase shifter

Modelling and analysis of scaled MOSFET devices and circuit simulation

Discussion on the performances of hybrid SET-MOSFET Voltage Controlled Oscillators

Reconfigurable nanoscale logic cells : a comparison study

Surface- potential- based model to study the subthreshold swing behavior including hot-carrier effect for nanoscale GASGAA MOSFETs

A dilated LMI approach to robust H∞ static state feedback controller synthesis

A chattering free control approach based on dynamical multi-sliding surfaces

Optimized joint NARX ANN - embedded processor design methodology

Fundamental logics based on two phase clocked adiabatic static CMOS logic

FPGA implementation of $I^{2}C$ & SPI protocols: A comparative study

Adaptive run-time power gating technique for low power IP core in SoC design

Implementation of a fixed-point FastSLAM 2.0 algorithm on a configurable and extensible VLIW processor

Study of different pulse waveforms and performance of TH-PPM Ultra Wideband Systems in multipath and multi-user environments simultaneously

A digital Cartesian feedback path design for 2.4GHz ISM band standards

VCO phase noise trade-offs in PLL design for DVB-T/H receivers

A new time-based architecture for serial communication links

A modified strategy of the common subexpression elimination and its application to implement FIR filters

Spectral purity analysis of integer-N PLL

Novel behavioral DAC modeling technique for WirelessHD system specification

A complete behavioral system model for a novel phase shifter technique

Prefilter bandwidth effects on the sequential symbol synchronizers based on pulse comparation

Time delay digital tanlock loop with linearized phase detector

Real time hardware implementation of a new Duffing's chaotic attractor

Generation of FARIMA(0,α,0) sequences by recursive filtering: Testing for self-similarity

Control of saturated systems with sliding mode

A novel hybrid Photovoltaic/Wave energy utilization system for island electricity

Novel linearizer for tangent/cotangent converter

Avalanche photodiodes for high energy particle tracking in 130 nm CMOS technology

A MEMS-based vacuum sensor with a PLL frequency-to-voltage converter

SPICE model for Piezoelectric Bender Generators

An adaptive oil stimulating device: Application for liquid-saturated reservoir

A glitch-corrector circuit for low-spur ADPLLs

A new linear voltage-to-current converter with threshold voltage compensation for analog circuits applications in polycrystalline silicon TFT process

An all-digital architecture for low-jitter regulated delay lines

A multiplexer-based digital passive linear counter (PLINCO)

A 40mW pseudo-differential 200MHz analog video pre-processing for HDTV flat-panel displays

Reduction parasitic capacitance in switching stage RF-CMOS Gilbert mixer for 2.4 GHz application

Noise optimization of a wideband capacitive shunt-shunt feedback LNA design suitable for software-defined radio

Low-power digitally-controlled variable gain LNA with high isolation for sub-GHz ISM bands

A dual mode 2.4-GHz CMOS low noise amplifier employing body biasing

A power optimized transconductance amplifier and its application to a $6^{th}$ order lowpass GmC filter

A low-area power-efficient CMOS active rectifier for wirelessly powered medical devices

Integration of polypyrrole microactuators and organic optoelectronic devices for lab-on-chip applications

Application of phased array systems to deep brain stimulation

Multithread RISC architecture based on programmable interleaved pipelining

A case study of improving at-speed testing coverage of a gigahertz microprocessor

A radiation hardened 512 kbit SRAM in 180 nm CMOS technology

High level modelling and performance evaluation of address mapping in NAND flash memory

An improved comparison circuit for low power pre-computation-based content-addressable memory designs

Degradation-aware analog design flow for lifetime yield analysis and optimization

Analysis and diagnosis of multiple simultaneous defects

A novel algorithm to extract open defects from industrial designs

Framework for statistical design of a flip-flop

Transmit processing with low resolution D/A-converters

Development of baseband processing SoC with ultrahigh-speed QAM modem and broadband radio system for demonstration experiment thereof

System design of bandpass sampling RF receivers

Clock recovery for a 40 Gb/s QPSK optical receiver

Wavelet image compression with CUDA

Development of aroma-Card based soundless Olfactory Display

NoC topology exploration for mobile multimedia applications

A multitransform architecture for the H.264/AVC standard and its design space exploration

Translinear signal processing circuits in standard CMOS FPAA

A new procedure and driver to control brushless micromotors

Application of combining classifiers for text-independent speaker identification

Design of an integrated analog controller for a class-D audio amplifier

A method reducing the time of RF test for Coupled Resonator Filters

Wideband 2.5 GHz VCO with active inductance in a 0.25 µm CMOS technology

Power efficient multimodulus programmable frequency divider with half-integer division ratio step size

Digital self-aware charge pump calibration technique for frequency synthesizers

A 312GHz fourth-harmonic voltage-controlled oscillator in 130nm SiGe BiCMOS technology

A 16-bit, 150-µW, 1-kS/s ADC with hybrid incremental and cyclic conversion scheme

A flexible resonation-based cascade ΣΔ modulator with simplified cancellation logic

Optimum selection of capacitive array for multibit Sigma-Delta modulators without DEM

Improved clock-phase generator based on self-biased CMOS logic for time-interleaved SC circuits

Low phase-noise VCO utilizing NMOS symmetric load for Frequency-based Delta-Sigma Modulators

Evaluating the performance of a configurable, extensible VLIW processor in FFT execution

Hardware implementation and power analysis of HWT for medical imaging

Dynamic voltage scaling based on supply current tracking using fuzzy Logic controller

Estimation of energy performance in computing platforms

A fast architecture for exhaustive search block matching algorithm with MPEG-4 applications

Placement and routing techniques to improve delay balance of WDDL netlist in MFPGA

Layout exploration of geometrically accurate arithmetic circuits

ADISI- An efficient tool for the automatic design of integrated spiral inductors

A post-layout optimization method with automatic device type selection for BiCMOS analog circuits

A CMOS amplitude detector for RF-BIST and calibration

Reducing handoff blocking probability in fourth generation wireless networks

Low power 4 x 5-Gb/s VCSEL driver array in 0.13-µm CMOS

Implementing the FTT-L protocol with ZigBee

Fairness and throughput optimization in wireless mesh networks

On-chip data compression for I.R. image sensors

Trust management in opportunistic pervasive healthcare systems

A Gigabit UDP/IP network stack in FPGA

Performance study of IEEE802.11e QoS in EDCF-contention-based static and dynamic Scenarios

Fuzzy-set based approach to compute optimum sizes of Voltage Followers

A semi - symbolic method of electronic circuit design by pole and zero distribution optimization using time - constants approximation

A cells and I/O pins partitioning refinement algorithm for 3D VLSI circuits

Symbolic formulation method for mixed-mode analog circuits using nullors

A Q-enhanced LC bandpass filter using CAIRO+

A new simply-designed scalar quantizer adaptable for any distribution

Complexity reductions in unrolled CORDIC architectures

A new penalty function for efficient detection criteria for the model order selection of interferometric SAR signals corrupted by multiplicative noise

Toward an optimal residual frame coding for DWT based video codec

Extended design of equiripple comb FIR filters

Voice singer detection in polyphonic music

Mapping method of reconfigurable cell matrices based on nanoscale devices using inter-stage fixed interconnection scheme

Two-dimensional analytical threshold voltage model for nanoscale graded channel gate stack DG MOSFETs

Predictive control of standalone brushless DC generators

A framework for offline optimization of energy consumption in real time multiprocessor system-on-chip

Modeling and simulation of electrical vehicle in VHDL-AMS

Notice of Violation of IEEE Publication Principles
Using matlab and Simulink in SystemC verification environment By JPEG algorithm

Low-cost Bayer to RGB bilinear interpolation with hardware-aware median filter

Comparison of the WLAN's security functions time consumption

Turbo channel estimation for an orthgonal space-time coded system on fast time-varying channels

RTS noise impact in CMOS image sensors readout circuit

Stability considerations in a new interface circuit for inductive position sensors

A 0.13µm CMOS VGA for drift chambers

Signal-to-noise ratio evaluation for embedded wireless sensor nodes: A novel methodology

A reliable and efficient power harvesting system in CMOS for bio-implantable devices

Design of A CMOS closed-loop system useful for bio-impedance measurements

Low-noise single-chip potentiostat for nano-bio-electrochemistry over a 1MHz bandwidth

Silicon millimeter-wave technologies and circuits

Circuits and system simulations for 100Gb/s optical SCM transmission

A combined 4-bit quadrature digital to analog converter/mixer for millimeter-wave applications

Millimeter-Waves building block design methodology in BiCMOS technology

Millimeter-wave passive components on silicon for wireless communication applications

A HW/SW mixed mechanism to improve the dependability of a stack processor

Elliptic Curve Point Multiplication in $GF(2^{n})$ using Polynomial Residue Arithmetic

A new RC design for mixed-grain based dynamically reconfigurable architectures

Performance measurements of synchronization mechanisms on 16PE NOC based multi-core with dedicated synchronization and data NOC

Analog design migration: An overview

A new methodology for constraint-driven layout design of analog circuits

Design flow for the generation of optimized FIR filters

Multi-pulse/single-pulse design for maximizing SIR in partially equalized OFDM systems over highly dispersive channels

A new scheme for preamble detection and frequency acquisition in OFDM systems

Amplify and forward relaying optimization for uplink CDMA communications subject to constant multiple access interference cost

Optimal training sequence length for soft iterative channel estimation

Performance improvement of UWB autocorrelation receivers by minimizing the energy capture time

ICECS 2009 author index

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A low power 0.13µm ADC for drift chambers

Content Provider	IEEE Xplore Digital Library
Author	D'Amico, S. De Matteis, M. Grancagnolo, F. Panareo, M. Perrino, R. Chiodini, G. Corvaglia, A. Cocciolo, G. Baschirotto, A.
Copyright Year	2009
Description	Author affiliation: INFN Sezione di Lecce, Italy (Grancagnolo, F.; Perrino, R.; Chiodini, G.; Corvaglia, A.; Baschirotto, A.) \|\| Department of Innovation Engineering - University of Salento, Italy (D'Amico, S.; De Matteis, M.; Panareo, M.; Cocciolo, G.)
Abstract	In this paper a 6 bits, 1GSa/s flash ADC is presented. It is included in a front end for drift chambers. The front-end has been designed in a 0.13µm CMOS technology with 1.2V supply voltage. The single circuit blocks are described in detail. The ENOB is 5.86bits, while the overall power consumption is 58.1mA.
Starting Page	407
Ending Page	410
File Size	633549
Page Count	4
File Format	PDF
ISBN	9781424450909
DOI	10.1109/ICECS.2009.5410904
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2009-12-13
Publisher Place	Tunisia
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Circuits Voltage CMOS technology Latches Energy consumption Ionization Clocks Technological innovation Power engineering and energy Signal processing
Content Type	Text
Resource Type	Article

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