NDLI: Asynchronous event redirecting in bio-inspired communication

Content Provider	IEEE Xplore Digital Library
Author	Hafliger, Ph.
Copyright Year	2001
Description	Author affiliation: Inst. of Informatics, Oslo Univ., Norway (Hafliger, Ph.)
Abstract	The paper presents the FPGA implementation of a programmable asynchronous digital circuit (henceforth called AE-map) that remaps 'address events'. Address event representation (AER) is an event driven communication protocol originally used in VLSI implementations of neural networks to transfer action potentials (neural voltage pulses) between neurons. More generally speaking it is suited to transmit a number of analog values that are coded in frequency of events over an asynchronous digital bus. The AE-map allows one to redirect such events between an AE sender and an AE receiver, thereby for instance programming the connection scheme of a neural network. Earlier approaches for redirecting AEs have used digital synchronous devices such as DSPs or microcontrollers. The simpler and more dedicated asynchronous solution presented here is more energy efficient, does not impose a discretization on the time axis and achieves a much faster throughput. In the present implementation AEs (9 bit input, 7 bit output) can be processed at intervals of less than 84 ns per output AE.
Sponsorship	IEEE CAS Soc. Univ. Malta
Starting Page	87
Ending Page	90
File Size	358520
Page Count	4
File Format	PDF
ISBN	0780370570
DOI	10.1109/ICECS.2001.957679
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2001-09-02
Publisher Place	Malta
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Neural networks Field programmable gate arrays Digital circuits Protocols Very large scale integration Voltage Neurons Frequency Digital signal processing Microcontrollers
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
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9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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