NDLI: A BGA package design of a read-out ASIC for GEM imaging detector

Content Provider	IEEE Xplore Digital Library
Author	Yuanyuan Pu Jian Cai Zhi Deng Yulan Li Xiaocui Zheng Shuidi Wang
Copyright Year	2010
Description	Author affiliation: Nuctech Co. Ltd. Beijing, 100084, China (Xiaocui Zheng) \|\| Dept. of Engineering Physics, Tsinghua University, Key Laboratory of Particle & Radiation Imaging (Tsinghua University), Ministry of Education, Beijing, 100084, China (Zhi Deng; Yulan Li) \|\| Institute of Microelectronics, Tsinghua University, Beijing 100084, China (Yuanyuan Pu; Jian Cai; Shuidi Wang)
Abstract	The ASIC involved in this paper is a read-out FET array for GEM imaging detector. In the ASIC, 4 (rows) × 8 (columns) units are implemented in an area of 2.5 mm × 2.5 mm. The ASIC is designed with a minimum readout cycle of 100 ns. As a read-out array for imaging detector, the package should be assembled in array form too, thus limits the package size. This paper would introduce the package design for this read-out ASIC, in which the substrate design is mainly focused on. The design limited in specific demands obeys the JEDEC design guide for fine-pitch BGA. The substrate is a 4-layer BT board, with two signal layers and two planes. For the package, designed ball size is 0.3mm. And the package height without attached solder balls is 1.06 +/−0.04 mm. After the process of substrate design and manufacture, die attach, wire bonding, molding, dicing and manual ball attachment, the package has been realized. The practical test for the package has been partially finished. Also the SI simulation is given out to compare with the results practical test brings out. With the results of SI simulation and practical test, the electrical performance of the designed package was evaluated.
Starting Page	687
Ending Page	690
File Size	849676
Page Count	4
File Format	PDF
ISBN	9781424481408
e-ISBN	9781424481422
DOI	10.1109/ICEPT.2010.5582860
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2010-08-16
Publisher Place	China
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Substrates Arrays Bonding Application specific integrated circuits Routing Pixel Wire
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Mr. Siddhartha Mukherjee siddhartha@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	ndl-support@iitkgp.ac.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Libarray of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

RUA: read-out unit ASIC for gamma ray detector readout

Dangling-wire avoidance routing for crossbar switch structured ASIC design style

GEMINI: A triple-GEM detector read-out mixed-signal ASIC in 180nm CMOS

A CMOS ASIC design for SiPM arrays

Triple metal routing methodology for ASIC sea-of-cells design

C-4/BGA comparison with other MLC single chip package alternatives

Performance-Driven Dual-Rail Routing Architecture for Structured ASIC Design Style

GEMINI, a CMOS 180 nm mixed-signal 16-channel ASIC for Triple-GEM detectors readout

AIDA: A 16-channel amplifier ASIC to read out the advanced implantation detector array for experiments in nuclear decay spectroscopy

A BGA package design of a read-out ASIC for GEM imaging detector

Similar Documents

RUA: read-out unit ASIC for gamma ray detector readout

Dangling-wire avoidance routing for crossbar switch structured ASIC design style

GEMINI: A triple-GEM detector read-out mixed-signal ASIC in 180nm CMOS

A CMOS ASIC design for SiPM arrays

Triple metal routing methodology for ASIC sea-of-cells design

C-4/BGA comparison with other MLC single chip package alternatives

Performance-Driven Dual-Rail Routing Architecture for Structured ASIC Design Style

GEMINI, a CMOS 180 nm mixed-signal 16-channel ASIC for Triple-GEM detectors readout

AIDA: A 16-channel amplifier ASIC to read out the advanced implantation detector array for experiments in nuclear decay spectroscopy

A BGA package design of a read-out ASIC for GEM imaging detector