NDLI: Optimized Micro-Via Technology for High Density and High Frequency (>40GHz) HermeticThrough-Wafer Connections in Silicon

Content Provider	IEEE Xplore Digital Library
Author	Hauffe, R. Kilian, A. Winter, M. Shiv, L. Elger, G. Heschel, M. Kuhmann, J. Isaacs, S. Weichel, S. Gaal, P. Korth, H. Hase, A.
Copyright Year	2005
Description	Author affiliation: Hymite GmbH, Berlin (Hauffe, R.; Kilian, A.; Winter, M.; Shiv, L.; Elger, G.; Heschel, M.; Kuhmann, J.; Isaacs, S.; Weichel, S.; Gaal, P.; Korth, H.; Hase, A.)
Abstract	We present the design, fabrication technology, and experimental evaluation of the high frequency performance of a new type of hermetically sealed through-wafer interconnects (mu-vias) in silicon substrates. The application of these mu-vias for wafer-scale hermetic packaging of receiver and transmitter optical subassemblies at 10Gbit/s, and for packaging of micro electro mechanical devices (MEMS) is discussed. These examples illustrate the potential of the technology to simplify the design of e.g. ball grid array packages (BGAs) in a cost effective way without sacrificing RF performance even at very high frequencies. Bandwidth measurements of the mu-via structures show reflections below -25dB up to 35GHz in a coplanar configuration even with multiple mu-vias in the path of a 50 Omega coplanar line. Additional losses due to the mu-vias are very low and below the detection limit of a 2.5mm long path. The waveguide losses were about 0.13dB/mm at 10GHz and about 0.28dB/mm at 40GHz. Excellent performance of the mu-vias is achieved by reducing their effective depth. On a 350mum or 500mum thick substrate the effective via depth can e.g. be reduced to only 20mum. The remaining depth is covered by impedance controlled coplanar lines that run down the slanted side wall of cavities in the silicon substrate. The concept thus combines the mechanical stability of substrates that are a few hundreds of microns thick with the ease to fabricate mu-vias in a membrane that is only a few tenths of microns thick. The pitch of these vias can be below 100 mum allowing for very high density interconnects as e.g. required in packaging of multi channel optical modules. The coplanar lines on the cavity side walls are realized by 3D photolithography using an electro-deposited photoresist and proximity exposure. The cavities with angled side walls are wet etched in aqueous KOH solution from one side of the substrate leaving a thin membrane in the bottom of the cavity (e.g. 20mum). This membrane is then opened up from the back side at the locations of the mu-vias in an additional KOH etching step. After structuring the metal lines the openings in the membranes are hermetically sealed by metal plating. The metallization scheme on which the vias and the electrical leads are based is compatible with reflow soldering and wire bonding. As an additional advantage the cavities can be enlarged and used as head room for discrete electro/optical components that are assembled on a lid wafer, or the components can be directly assembled in the cavity. Coplanar metal lines in combination with the proposed via technology allow the impedance matched connection of these high speed components to a ball grid array (BGA) on the back side of the hermetic enclosure which in turn can be soldered to a rigid circuit board or to a flexible circuit board. Due to the tight control of tolerances and the dense via pitch it is easily possible to route multiple RF ports in and out of the package even in differential configurations and with additional DC control signals while still maintaining a very small footprint and excellent signal integrity. The presented via technology is not only able to fulfill today's requirements in hermetic and cost effective packaging of high bit rate electro/optical modules but scales to bit rates above 40GHz and to packages with very large numbers of I/O counts
Starting Page	324
Ending Page	330
File Size	1295525
Page Count	7
File Format	PDF
ISBN	0780389077
ISSN	05695503
DOI	10.1109/ECTC.2005.1441286
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2005-05-31
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Frequency Silicon Biomembranes Optical receivers Optical transmitters Hermetic seals Optical devices Optical interconnections Electronics packaging Costs
Content Type	Text
Resource Type	Article
Subject	Electronic, Optical and Magnetic Materials Electrical and Electronic Engineering

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Mr. Siddhartha Mukherjee siddhartha@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	ndl-support@iitkgp.ac.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Libarray of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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