NDLI: Stacked thin dice packaging

Content Provider	IEEE Xplore Digital Library
Author	Pienimaa, S.K. Valtanen, J. Heikkila, R. Ristolainen, E.
Copyright Year	2001
Description	Author affiliation: Tampere Univ. of Technol., Finland (Pienimaa, S.K.)
Abstract	This paper reports on a developed stacking method to produce a small volume three-dimensional package. The first part of the 3/sup rd/ dimension is tackled by reducing package thickness and also the stand-off height. The steps came through thinning dice, using a thin interposer, and to stack the components. The thickness of the used ICs was 90 /spl mu/m, whereas typically thicknesses are around 250-300 /spl mu/m. Thin dice were connected through eutectic solder bumps on thin aramid epoxy substrates. The package was studied with the finite element method (FEM) using three-dimensional (3-D) models and the Ansys program. The average plastic work in the solder bump was used to define the reliability of the structure. Structures with one to four layers are compared. In current flip-chip assemblies, rigidity assists good electrical performance and reliability. Reducing the IC thickness below 100 /spl mu/m creates new challenges for handling, interconnecting, reliability and design. These tasks have been addressed in this study. The designed circuits for the above tests have been characterized and more details of the results are presented. Further progress in density increase has been achieved by stacking layers of flexible substrate and thin die on top of each other. For this work, the first level connection has been flip-chip bonding. The goal was to develop a method to produce modules on a small scale to verify the feasibility of various System-in-Package (SiP) solutions. The method has been tested using thin dice, mainly daisy chain. Devices are miniaturized to be more comfortable to carry; this size reduction desire, together with increased functionality, have become drivers, especially for wireless devices. Size reduction of electronics has set a challenge for packaging and provided the motivation to verify emerging technologies.
Sponsorship	Components, Packaging, & Manuf. Technol. (CPMT) Soc. IEEE
Starting Page	361
Ending Page	366
File Size	835526
Page Count	6
File Format	PDF
ISBN	0780370384
ISSN	05695503
DOI	10.1109/ECTC.2001.927749
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2001-05-29
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Electronics packaging Stacking Silicon Chip scale packaging Space technology Circuit testing Bonding Driver circuits Finite element methods Plastics
Content Type	Text
Resource Type	Article
Subject	Electronic, Optical and Magnetic Materials Electrical and Electronic Engineering

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3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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