NDLI: Latchup-free CMOS structure using shallow trench isolation

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Plenary session—Invited papers

Silicon sensor technologies

The free electron laser—Historical perspective, current status and future prospects

The technological requirements for application specific integrated circuits

Session 2 Device technology — Bipolar structures and technology

Prospects of SST technology for high speed LSI

Hot carrier effects in advanced self-aligned bipolar transistors

A new self-aligned bipolar transistor using vertical nitride mask

Impact of processing parameters on base current in polysilicon contacted bipolar transistors

A sub-100 picosecond bipolar ECL technology

A new "SICOS" Schottky device

High capacitance ultra-thin Ta2O5dielectric film applied to a high-speed bipolar memory cell

Session 3 Solid state devices — Hot-carrier effects

Hot-electron degradation in submicron VLSI

Characterization of Si/SiO2interface degradation due to hot-carrier injection

Experimental determination of hot-carrier energy distribution and minority carrier generation mechanism due to hot-carrier effects

High field effects in MOSFETS

Trap generation in gate oxide layer of MOS structures encapsulated by silicon nitride

High frequency noise in fine line NMOS field effect transistors

Two-dimensional modeling of channel hot-electron effects in silicon MOSFETS

Session 4 Quantum electronics and compound-semiconductor devices — High speed III-V semiconductor devices

Using silicon device modeling techniques for GaAs devices

A high transconductance GaAs MESFET with reduced short channel effect characteristics

GaAs FET with a degenerate semiconductor gate

A high density GaAs static RAM process using MASFET

A 1GHz-5mA/5V dual modulus GaAs prescaler IC

Planar-type InAs-coupled three-terminal superconducting devices

Reproducible fabrication of high-performance GaAs permeable base transistors

Optically induced, spatially resolved backgating transients in GaAs FETs

Session 5 Detectors, sensors and displays — Solid-state sensors and displays

Frontiers in solid state biomedical transducers

Optical fiber sensor technology

New integrated polysilicon photoconductor for ultrafast measurements on silicon

Heteroepitaxial PbTe-Si and (Pb, Sn)Se-Si structures for monolithic 3-5 µm and 8-12 µm infrared sensor arrays

Light-induced persistence of leakage current and low frequency noise in reverse biased backside-illuminated Hg1-xCdxTe photodiodes

A high sensitivity solid state sensor for H2detection in oxygen-rich ambients at room temperature

Integrated Zinc oxide-on-silicon tactile-sensor array

Nonlinear analyses on CMOS integrated silicon pressure sensor

Session 6 Solid state devices — Discrete power devices

An advanced high voltage bipolar power transistor with extended RBSOA using 5 µm small emitter structures

A self-aligned short process for insulated gate transistors

Experimental and numerical study of non-latch-up bipolar-mode MOSFET characteristics

Variation of lateral doping—A new concept to avoid high voltage breakdown of planar junctions

MOS GTO—A turn off thyristor with MOS-controlled emitter shorts

Improved dynamic properties of GTO-thyristors and diodes by proton implantation

A 2.45 GHz power LD-MOSFET with reduced source inductance by V-groove connections

Session 7 Electron tubes — New technology, guns and codes

Vacuum integrated circuits

Transient analysis of beam interaction with antisymmetric mode in truncated periodic structure using 3-dimensional computer code "SOS"

A new interpretation of the time evolution of the RF electric field in a crossed-field device

Simulation of space-charge effects on velocity spread in gyro devices

Ultralaminar 250 kV gun for fast-wave devices

Tunnel emittance growth in PPM focussed TWT's

An ultrahigh precision electron gun-tube alignment technique for millimeter-wave applications

Session 8 Device technology — Novel device technology

A trench MOSFET with surface source/drain contacts

A novel MOS device structure with S/D contacts over oxide (COO)

Novel submicron MOS devices by self-aligned nitridation of silicide (Sanicide)

Fabrication and characterization of sub-micron thin gate oxide p-channel transistors with p+ polysilicon gates

A 600°C process for MOSFET fabrication using microwave plasma-stream gate oxidation

LPCVD In-situ arsenic doped polysilicon for VLSI applications

Microwave annealing for low temperature VLSI processing

Session 9 Solid state devices — LDD device structures

Halo doping effects in submicron DI-LDD device design

Modified LDD device structures for VLSI

Relief of hot carrier constraint on submicron CMOS devices by use of a buried channel structure

Lightly doped drain structure for advanced CMOS (Twin-Tub IV)

Reliability and performance of submicron LDD NMOSFET's with buried As $n^{-}impurity$ profiles

A new degradation mechanism of current drivability and reliability of asymmetrical LDDMOSFET's

Increase of resistance to hot carriers in thin oxide MOSFETS

Session 10 Integrated circuits: Advanced circuit technologies

Advanced analog CMOS technology

A submicron NMOS technology suitable for low power high speed circuits

Investigation of cryogenic CMOS performance

A sub-200 picosecond GaAs sample-and-hold circuit for a multi-gigasample/second integrated circuit

A silicon magneto-coupler using a carrier-domain magnetometer

A new high density full CMOS SRAM cell using polysilicon interconnection structure

Dynamic cross-coupled bitline content addressable memory cell for high density arrays

Session 11 Solid state devices — Advanced bipolar devices

Simultaneous measurement of hole lifetime, hole mobility and bandgap narrowing in heavily doped n-type silicon

A novel structure amorphous SiC:H emitter HBT using low temperature process

A dual buried layer technology for the fabrication of high voltage NPN devices compatible with a 1.5 micron epitaxial bipolar process

Base current analysis of poly-Si emitter bipolar transistors

A model-base comparison: GaAs/GaAlAs HBT versus silicon bipolar

Probe-device detecting single carriers: A new method for deep level characterization with nanosecond resolution

Session 12 Quantum electronics and compound-semiconductor devices — High speed heterojunction devices

Wave function dependent electron transport in N-AlGaAs/GaAs heterostructures and its applications to velocity modulation transistor (VMT) and switch (VMS)

Complementary heterostructure insulated gate field effect transistors (HIGFETs)

DC and microwave performance of In0.53Ga0.47As-In0.52Al0.48As single quantum well MISFETS

GaAs/GaAlAs high electron mobility transistors for analog-to-digital converter applications

AlGaAs/GaAs heterojunction bipolar transistors

GaAs/AlGaAs heterojunction bipolar transistors on Si substrates

High-frequency characterization of the charge injection transistor

Session 13 Electron tubes — Linear beam devices

Pre-bunched beam devices—Efficient sources of UHF and microwave power

Long-life travelling-wave tubes use of "M" type cathode life prediction model

π-Line high power TWT's

Microwave physics of flame-sprayed Kanthal and other circuit loss coatings

RF beam spread in PPM confined-flow TWTs

TWT Efficiency enhancement with textured carbon surfaces on copper MDC electrodes

Submillimeter-wave BWO's

Session 14 Device technology — Dielectrics and isolation

Thin oxide reliability

Analysis of defects in thin SiO2thermally grown on Si substrate

Electrical characteristics of thin gate implanted MOS channels grown by rapid thermal processing

Studies of thin poly Si oxides for E and $E^{2}PROM$

Properties of trench capacitors for high density DRAM applications

Two-dimensional silicon oxidation experiments and theory

Scaling limitations of submicron local oxidation technology

Session 15 Device technology — Advanced CMOS technology

Process and device considerations for micron and submicron CMOS technology

A new process for one micron and finer CMOS

Formation of 0.1 µm $N^{+}/P$ and $P^{+}/N$ junctions by doped silicide technology

The impact of TiSi2 on shallow junctions

Lightly impurity doped (LD) Mo silicide gate technology

1/4µm CMOS isolation technique with sidewall insulator and selective epitaxy

High speed BiCMOS VLSI technology with buried twin well structure

Session 16 Detectors, sensors and displays — Displays and image sensors

Silicon thin film devices for displays—Status and directions

Amorphous silicon bipolar transistor with high gain (>12) and high speed (>30µs)

a-Si:H TFT array driven linear image sensor with capacitance coupling isolation structure

The operational characteristics of a static induction transistor(SIT) image sensor

1/2-Inch 768(H)×492(V) pixel CCD image sensor

Deep-depletion CCDs with improved UV sensitivity

Partition noise in CCD signal detection

Session 17 Quantum electronics and compound-semiconductor devices — Photodetectors and optical sampling

Multiple quantum well devices for optoelectronics

New high speed long wavelength Al0.48In0.52As/Ga0.47In0.53As multiquantum well avalanche photodiodes

Planar InGaAs/InP photodiodes grown by metalorganic chemical vapor deposition

Picosecond photodetectors fabricated in GaAs layers grown on silicon and silicon-on sapphire substrates

Gain noise reduction in InGaAs photoconductive detectors by hole sweep-out effect

High conversion efficiency and radiation resistant InP solar cell

Characterization of GaAs integrated circuits by direct electro-optic sampling

Picosecond optical autocorrelation measurements on single optoelectronic devices

MOS Device modeling for circuit simulation

Analysis of LDD transistor asymmetry susceptibility in VLSI circuits

A full three-dimensional simulation on alpha-particle induced DRAM soft-errors

A direct SRAM soft-error cross-section simulation with two-dimensional transport calculations

Static and transient latch-up hardness in N-well CMOS with on-chip substrate bias generator

Latchup-free CMOS structure using shallow trench isolation

A highly latchup-immune 1 µm CMOS technology fabricated with 1 MeV ion implantation and self-aligned TiSi2

Floating well CMOS and latchup

Session 19 Electron tubes — Fast wave tubes

High power gyrotrons in the 100 GHz to 150 GHz frequency range

Development of high frequency gyrotrons

Design of a 34.5 GHz 400 kilowatt CW gyroklystron amplifier

The theory and operation of a multicavity high-harmonic gyro-klystron amplifier

Self-consistent large theory and simulation of high harmonic gyrotron and peniotron oscillators operating in a magnetron-type cavity

The cyclotron maser and beam boundary conditions

Gyroklystrons—A new concept in high power tubes

A high repetition rate compact 94GHz free electron laser

Session 20 Impact of technology advances on CMOS circuit design

Session 21 Hot carrier effects in MOS for VLSI

Session 22 Integrated sensor electronics

Session 23 Quantum-well and superlattice active electronic devices

Session 24 Solid state devices — Novel MOS operation and configuration

Quantum mechanical effects in very short and very narrow channel MOSFETs

Application of the Shubnikov-de Haas effect in characterization of sub-100-NM channel SI MOSFETs

Low-temperature substrate current characterization of N-channel MOSFET's

Transient substrate current generation and device degradation in CMOS circuits at 77K

Substrate current in N-channel and P-channel MOSFETs between 77K and 300K: Characterization and simulation

Optimum crystallographic orientation of submicron CMOS devices

Effects of silicon surface orientation on submicron CMOS devices

Session 25 Device technology — Contact and interconnect technology

2-D Simulations for accurate extraction of the specific contact resistivity from contact resistance data

VLSI Local interconnect level using titanium nitride

Laser direct writing of metal interconnects

X-Ray lithography for 0.5µm VLSI: Assessment of mask accuracy, patterning and damage

A novel borophosphosilicate glass process

Creep-up phenomena in tungsten selective CVD and their application to VLSI technologies

Highly reliable one-micron-rule interconnection utilizing TiN barrier metal

Session 26 Integrated circuits — Non-volatile memory technology

A single transistor EEPROM cell and its implementation in a 512K CMOS EEPROM

A 256K high performance CMOS EEPROM technology

The effects of write/erase cycling on data loss in EEPROMs

A high performance memory cell technology for mega bit EPROMS

A high performance CMOS technology for 256K/1MB EPROMs

A new EPROM cell with a side-wall floating gate for high-density and high-performance device

A new programmable cell utilizing insulator breakdown

Session 27 Quantum electronics and compound semiconductor devices — Optoelectronics and resonant tunneling

Ultra-high speed semiconductor lasers

A novel self-aligned AlGaAs laser with bent active layer grown by MOCVD

Optoelectronic integrated transmitter with a microcleaved facet AlGaAs/GaAs quantum well laser

Dynamic switch logic — A new concept for digital optical logic using DOES devices

High performance AlGaAs visible (700 nm) LED on Si substrate prepared by MOCVD

Room temperature operation of high-performance AlAs/GaAs/AlAs resonant tunneling diodes with atomically controlled barrier width

Mechanism of operation of double-barrier resonant-tunneling ocsillators

Session 28 Device technology — SOI technologies

Characteristics of submicrometer CMOS transistors in implanted-buried-oxide SOI films

A high-speed submicrometer CMOS/SOS process in spear material

Si-Gate CMOS devices on a Si/CaF2/Si structure

Silicon-on-insulator (SOI) by bonding and ETCH-back

Novel LSI/SOI wafer fabrication using device layer transfer technique

Session 29 Integrated circuits — Advanced DRAM technologies

Cell structures for future DRAM's

Technology for the fabrication of A 1 MB CMOS DRAM

A deep-trenched capacitor technology for 4 mega bit dynamic RAM

Submicron CMOS technologies for four mega bit dynamic RAM

Buried storage electrode (BSE) cell for megabit DRAMs

A trench transistor cross-point DRAM cell

A three-dimensional DRAM cell of stacked switching-transistor in SOI (SSS)

Session 30 Solid state devices — High voltage integrated circuits and devices

Approaches to isolation in high voltage integrated circuits

350V analog-digital compatible power IC technologies

Integrable high voltage CMOS: Devices, process application

Comparison of lateral and vertical DMOS specific on-resistance

Analysis of the lateral insulated gate transistor

Lateral insulated gate transistors with improved latching characteristics

Experimental superconducting-base transistor

High performance In0.15Ga0.85As/Al0.15Ga0.85As quantum well modulation doped FETs

A CMOS device isolation structure using the selective-etch-and-refill-with-EPI (SEREPI) process

1.3µm Operation of GexSi1-x/Si strained-layer superlattice avalanche photodetectors

Extremely high transconductance (above 500 mS/mm) MOSFET with 2.5 nm gate oxide

Observation of negative conductance by sequential resonant tunneling through a one micron thick superlattice

Monolithic integration of Si MOSFETs and GaAs MESFETs

Fabrication and properties of n-channel SiGe/Si modulation doped field-effect transistors grown by MBE

The SPT cell—A new substrate-plate trench cell for DRAMs

1984 International Electron Devices Meeting

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Latchup-free CMOS structure using shallow trench isolation

Content Provider	IEEE Xplore Digital Library
Author	Niitsu, Y. Taguchi, S. Shibata, K. Fuji, H. Shimamune, Y. Iwai, H. Kanzaki, K.
Copyright Year	1985
Description	Author affiliation: Toshiba Corporation, Kawasaki, Japan (Niitsu, Y.)
Abstract	Using a shallow trench and a thin epitaxial layer, latchup-free CMOS has been realized. When the trench depth is 1.4 µm and the epitaxial layer thickness is 2 µm, the latchup holding voltage, VHis higher than 13 V. The mechanism of VHincrease is discussed using an equivalent circuit including the reverse transistors of the parasitic bipolar transistors. The interruption of lateral current flow with the trench contributes to VHincrease. From the results, it is well expected that the only about 1 µm deep trench must be adequate for achieving VHhigher than the supply voltage, i.e. 5V, and that the fabrication process of trench isolation becomes more reliable and easier.
Starting Page	509
Ending Page	512
File Size	271027
Page Count	4
File Format	PDF
DOI	10.1109/IEDM.1985.191015
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1985-12-01
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Epitaxial layers Voltage Thyristors Substrates Power supplies Isolation technology Etching Circuit testing Boron Semiconductor devices
Content Type	Text
Resource Type	Article

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